CODEWITHSUNDEEP
verilogsystem-verilog
shaharhoch
shaharhoch

Reputation: 115

Verilog: Accessing wire in sub-module instance

I would like to know if there is a syntax in Verilog to access a wire in a sub-module without making that wire an output.

For example, if have the following modules: 

module Module_Sub(a,b);
   input a,b; 
   wire c; 
   ...
endmodule


module Module_Top(d, e);
   input d,e; 
   wire f; 

   Module_Sub sm(d,e); 
   ...
endmodule

Now, I want to access the wire 'c' in the instance 'sm' from the scope of Module_Top. Is there a way to do it? maybe something like: 

assign f = sm/c;

(This syntax obviously didn't work for me).

P.S: I know this isn't the best practice, but in my case it will make things a lot easier.

Thanks!

edit: I want it for a synthesis-able code.

Upvotes: 0

Views: 6567

Answers (1)

toolic
toolic

Reputation: 62045

You were very close. Use dot, not slash:

module Module_Sub(a,b);
   input a,b; 
   wire c; 
endmodule

module Module_Top(d, e);
   input d,e; 
   wire f = sm.c; 

   Module_Sub sm(d,e); 
endmodule

Refer to IEEE Std 1800-2012, section 23.7 "Member selects and hierarchical names".

Upvotes: 0

Related Questions