CODEWITHSUNDEEP
verilogsystem-verilog
user125535
user125535

Reputation: 262

8 bit wide, 2-to-1 multiplexer verilog module

I'm having a lot of trouble making any sort of sense of this problem. I'm supposed to create a module for an 8 bit wide 2-to-1 multiplexer using Verilog.

The question:

Write a verilog module that uses 8 assignment statements to describe the circuit. Use SW[17] on the DE2 board as the s input, switches [7:0] as the X input, switches [15:8] as the Y input. Connect SW switches to the red lights LEDR and output M to the green light LEDG [7:0].

My code:

module example(M, X, Y, S)

    input[15:0] SW;
    input SW[17];

    output [7:0] LEDR;
    output [7:0] LEDG;
    output [7:0] M;

    wire [7:0] X = SW[7:0];
    wire [7:0] Y = SW[15:8];
    wire S = SW[17]

    assign M[0] = X[0] & ~S | Y[8] & S;
    assign M[1] = X[1] & ~S | Y[9] & S;
    assign M[2] = X[2] & ~S | Y[10] & S;
    assign M[3] = X[3] & ~S | Y[11] & S;
    assign M[4] = X[4] & ~S | Y[12] & S;
    assign M[5] = X[5] & ~S | Y[13] & S;
    assign M[6] = X[6] & ~S | Y[14] & S;
    assign M[7] = X[7] & ~S | Y[15] & S;

endmodule

I don't understand how I'm supposed to assign m to the green LEDG[7:0] since I've already assigned each M to those conditional statements. Anyone know how to get around this?

Upvotes: 1

Views: 8814

Answers (1)

Unn
Unn

Reputation: 5108

While there are multiple ways to do this, I suggest make a wrapper module containing the board i/o as inputs and outputs and instantiate your MUX inside of it:

module top(input [17:0]  SW,
           output [15:0] LEDR,
           output [7:0]  LEDG);

  example ex(.M(LEDG), .s(SW[17]), .X(SW[7:0]), .Y(SW[15:8]));

  assign LEDR[7:0] = X;
  assign LEDR[15:8] = Y;

endmodule

[insert your mux module minus the board i/o here]

If you cannot use the above solution, you can look up how to use the Pin Planner in QuartusII (which I assume you are using from the DE2 reference in your prompt).

Upvotes: 1

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