Reputation: 15
I need create 8*1 multiplexer by 2-1 multiplexer. At this time, my code can work. However, the output is incorrect. And the wires O_0.O_1,O_2,O_3 can work correctly. When the 2-1 multiplexer read the selector [1] and [2], it does not change. The output is between I0 AND I1. Can you help me with the problem? Or just tell me where the mistake is?
This is not italic `
module MUX_8_1 (i0 ,i1 ,i2 ,i3 ,i4 ,i5 ,i6 ,i7 , selectors , o_8 );
input [31:0] i0 ,i1 ,i2 ,i3 ,i4 ,i5 ,i6 ,i7;
input [2:0] selectors ;
output [31:0] o_8 ;
wire [31:0] o_0;
wire [31:0] o_1;
wire [31:0] o_2;
wire [31:0] o_3;
wire [31:0] o_4;
wire [31:0] o_5;
MUX_2_1 M1(.i0 (i0), .i1 (i1), .sel (selectors[0]),.o (o_0));
MUX_2_1 M2(.i0 (i2), .i1 (i3), .sel (selectors[0]),.o (o_1));
MUX_2_1 M3(.i0 (i4), .i1 (i5), .sel (selectors[0]),.o (o_2));
MUX_2_1 M4(.i0 (i6), .i1 (i7), .sel (selectors[0]),.o (o_3));
MUX_2_1 M5(.i0 (o_0), .i1 (o_1), .sel (selectors[1]),.o (o_4));
MUX_2_1 M6(.i0 (o_2), .i1 (o_3), .sel (selectors[1]),.o (o_5));
MUX_2_1 M7(.i0 (o_4), .i1 (o_5), .sel (selectors[2]),.o (o_8));
endmodule
module MUX_2_1 (i0 ,i1 ,sel ,o);
input [31:0] i0 ,i1;
input sel ;
output [31:0] o;
assign #19 o = (i0 & (~sel)) | (i1 & sel);
endmodule`
This is not italic
module MUX_8_1_TB;
// Inputs
reg [31:0] i0;
reg [31:0] i1;
reg [31:0] i2;
reg [31:0] i3;
reg [31:0] i4;
reg [31:0] i5;
reg [31:0] i6;
reg [31:0] i7;
reg [2:0] selectors;
// Outputs
wire [31:0]o_8;
// Instantiate the Unit Under Test (UUT)
MUX_8_1 uut (
.i0(i0),
.i1(i1),
.i2(i2),
.i3(i3),
.i4(i4),
.i5(i5),
.i6(i6),
.i7(i7),
.selectors(selectors),
.o_8(o_8)
);
initial begin
i0 = 32'b1000;
i1 = 32'b1001;
i2 = 32'b1010;
i3 = 32'b1011;
i4 = 32'b1100;
i5 = 32'b1101;
i6 = 32'b1110;
i7 = 32'b1111;
selectors = 3'b000;#100;
selectors = 3'b001;#100;
selectors = 3'b010;#100;
selectors = 3'b011;#100;
selectors = 3'b100;#100;
selectors = 3'b101;#100;
selectors = 3'b110;#100;
selectors = 3'b111;#100;
end
endmodule
Upvotes: 0
Views: 2055
Reputation: 2002
I believe, assign statement in the MUX_2_1 is not proper.
You have 2 options to rectify it.
1st Option
You can use ternary operator (which is more preferable, as per my opinion)
assign o = (sel) ? (i1) : (i0);
2nd Option
It seems that, you wrote this code, by considering the actual gate level schematic or netlist of the 2*1 mux.
But to mimic, the actual gate level design, you should consider ANDing of the individual bits of the i0, i1 nets.
So your code may look like this :
assign o[0] = (i0[0] & ~sel) | (i1[0] & sel);
assign o[1] = (i0[1] & ~sel) | (i1[1] & sel);
assign o[2] = (i0[2] & ~sel) | (i1[2] & sel);
// Similarly for all 32 bits
assign o[31] = (i0[31] & ~sel) | (i1[31] & sel);
Now, you may wonder that, you need to copy same statement 32 times!!!!.
So you have an alternative for this :
genvar c;
generate
for (c = 0; c < 32; c = c + 1)
begin: test
assign o[c] = (i0[c] & ~sel) | (i1[c] & sel);
end
endgenerate
Upvotes: 0
Reputation: 487
Its your 2:1 Mux logic seems to be flawed. Try
assign o = (sel) ? i1 : i0;
Upvotes: 1