CODEWITHSUNDEEP
system-veriloghdl
Sébastien Baillou
Sébastien Baillou

Reputation: 31

SystemVerilog generic multiplexer

I am trying to come up with a way to define a synthesizable generic multiplexer (either as a function or module) that can be used with wires, and typedefs (enums, structs) in SystemVerilog

Is that possible in any way? If not, what would be the cleanest approach to write such a multiplexer?

Currently, I am using a multiplexer that takes a two-dimensional array of wires as input and selects one of the elements based on a select signal.

This makes it rather painful as I am stuck casting my typed variables back and forth every time I need to connect them to the multiplexer module. And sadly, this is made even worse by the fact that a for loop is needed to assign a array of typed elements into an array of wires.

Thanks, Sébastien.

Upvotes: 1

Views: 1708

Answers (1)

Sébastien Baillou
Sébastien Baillou

Reputation: 31

Well, looks like I'll be able to help myself today.

SystemVerilog allows parameterization of modules with types using the "parameter type" feature. This does exactly what I'm looking for, and seems to be supported by the common vendors.

module mux #(
  parameter type T = logic,
  parameter SIZE = 2)
(
  input  wire [SIZE-1:0] select,
  input  wire T          in [SIZE-1:0],
  output wire T          out
);

Then, the back & forth type casting and actual muxing can be performed within the module, which cleans up the rest of the code.

Upvotes: 2

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