CODEWITHSUNDEEP
vhdl
Nish
Nish

Reputation: 13

D flip flop with a feedback loop to clear

Here is my code for a d flip flop with active low asynchronous clear and reset. Clear has a an input which is a combination of q (output of d ff) and the reset signal.I have uploaded an image to show you the circuit for which I have written this program. I do not get the expected output; clear and q is always low. I have set reset as logic one in the simulation. Please help and let me know my mistake :) Thank you.

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
use ieee.numeric_std.all;


ENTITY d_feedback_clr IS
PORT ( 
       clock, reset, d: IN STD_LOGIC ;  
       q : OUT STD_LOGIC
      ) ;

END d_feedback_clr ;

ARCHITECTURE Behavior OF d_feedback_clr IS
signal state, clear: STD_LOGIC:='0'; -- state implies the output of the d register

BEGIN

    clear <= reset nand state; 

    PROCESS (clock, clear, reset)
        BEGIN

             IF (clear='0') THEN
                state <= '0';
             elsif reset='0' then
                state <= '1'; 
             elsif (clock'event and clock='1') THEN
                state <= d;                                     
             END IF ;

    END PROCESS ;
    q <= state;
END Behavior ;

Upvotes: 0

Views: 1422

Answers (1)

Duy Anh Trần
Duy Anh Trần

Reputation: 36

I think your problem is in the clear signal. If your state is '1' and reset is '1' then clear signal, as the output of a nand gate of these two, will become '0' and the state will immediately change to '0'. So the state and q will always be low.

I've used Modelsim Altera to simulate your design, and it clearly showed glitches in the signal.

Simulation result

Upvotes: 2

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