CODEWITHSUNDEEP
verilogfpga
underhiscanvas
underhiscanvas

Reputation: 37

Always block instead of assign, simulated in FPGA

I am trying to code and synthesize in Verilog. Sometimes I am still getting confused with using Verilog as a typical C like programming language, I am trying to understand if there will be a difference between 2 different codes:

always @ (a1,a0,b1,b0)
begin
case ({a1,a0,b1,b0})
                 4'b0000 : s= 7'b1110111 ;
                 4'b0001 : s= 7'b1110111  ;
                  ....
                  ....
                 4'b1110 : s= 7'b0101111  ; 
                 4'b1111 : s= 7'b1111010 ;
                 endcase


    end

and

using the above code logic with assign, instead of always block.

Will the above code generate a latch? In which case would it generate a latch? Will there be any delay difference between using the 2 codes?

PS we are trying to create a 2bit binary multiplier, which outputs to a 7 segm display. Thank you.

Upvotes: 0

Views: 342

Answers (1)

wilcroft
wilcroft

Reputation: 1635

Latches are generated when one or more paths through a conditional statement are unassigned. For example:

reg [1:0] a;
reg b;
always@(*)
case (a)
    0: b=0;
    1: b=0;
    2: b=1;
endcase

would generate a latch, because I did not cover the a=3 case. You can avoid this by either explicitly covering each case (like it appears you have done) or by using the default case.

For assign statements, it depends on how you format them, but you're significantly less likely to accidentally infer a latch. For example, if you you the ternary operation (i.e. assign b = a? 1:0;) both halves of the if are inferred.

As for delay, case vs. assign should create the same netlist, so they should produce similar or identical results, provided they're logically identical.

(As a side note, it's good practice to use always@(*), rather than always @ (a1,a0,b1,b0); The synthesis tool can figure out the correct sensitivity list.)

Upvotes: 3

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