Reputation: 1
I am trying to process LU decomposition in VHDL. I am a starter in VHDL. So I started implementing LU decomposition algorithm in MATLAB.
a = [1 2 2;3 4 4;5 6 6];
x=a;
n=size(x,1);
l=zeros(n,n);
u=zeros(n,n);
for k=1:n
if (a(k,k)~=0)
u(k,k)=x(k,k);
l(k,k)=1;
for i=k+1:n
l(i,k)=x(i,k)/x(k,k);
u(k,i)=x(k,i);
end
for i=k+1:n
for j=k+1:n
x(i,j)=x(i,j)-(l(i,k)*u(k,j));
end
end
else break
end
end
Then I started doing this without for loop because for loop in vhdl doesn't work like matlab. Now, I am facing problem finding the equivalent code for the cascaded for loop.
a = [1 2 2;3 4 4;5 6 6];
x=a;
n=size(x,1);
l=zeros(n,n);
u=zeros(n,n);
k=1;
m=2;
j=2;
p=2;
for clock=1:100
if k>=1 && k<=n
if (a(k,k)~=0)
u(k,k)=x(k,k);
l(k,k)=1;
else disp('Decomposition not possible')
return
end
if (m>=k+1 && m<=n)
l(m,k)=x(m,k)/x(k,k);
u(k,m)=x(k,m);
m=m+1;
end
if p>=k+1 && p<=n
if j>=k+1 && j<=n
x(p,j)=x(p,j)-(l(p,k)*u(k,j));
j=j+1;
end
if j==n+1
p=p+1;
j=2;
end
end
end
k=k+1;
end
I know the last code is not equivalent to the previous one. Can someone please help me with some hint on doing this in VHDL?
Upvotes: 0
Views: 465
Reputation:
Captain Obvious to the (title) rescue:
A = [1 2 2;3 4 4;5 6 6];
[L,U] = lu(A);
As for the actual question "can one implement a loop with if
/else
instead of for
/while
" (not very well reflected in the title though): yes, it is possible if the language allows goto
statements. Loops are basically (un)conditional jumps back in the statement "stream". MATLAB is not one of those languages.
In a C-like language you can implement (declarations aside) a basic for
loop like this:
k = 0;
enter_loop:
if(k < n) {
/* here do in-loop stuff */
k = k+1;
goto enter_loop;
}
Note: Your problem seems to be with VHDL. Why don't you change the question tags so VHDL people can answer it directly?
Upvotes: 2