CODEWITHSUNDEEP
vhdl
Ashwin Mertes
Ashwin Mertes

Reputation: 1

Simulation not working - port mapping wrong?

VHDL code

First of all, sorry for the redirect, but it's easier that way. I'm building a digital clock, but as you can see, clock_AN and clock_seg_out do not change. Is this caused by a wrong port mapping? Thanks!

Upvotes: 0

Views: 212

Answers (1)

Marty
Marty

Reputation: 6644

Your input master clock is too slow. Looking at the frequency divider cct, it looks like you've it programmed to divide a 100MHz clock. So either:

  • speed up your testbench master clock
  • or set the divider target to a lower number for debug purposes

Go with #2 if you want reasonable sim times!

Upvotes: 1

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