CODEWITHSUNDEEP
verilog
Wakeel Ahmed
Wakeel Ahmed

Reputation: 1

Error in Function evaluation

module ff(fv,a,b,c);
output [9:0]fv;
input [4 : 0] a,b,c;  
reg [4 : 0] x[9 : 0];
reg [9 : 0] np[9 : 0];
reg [4:0] newpop;
reg [4 : 0] y;

genvar i;

initial
begin
   x = { 4, 7, 2, 5, 4, 5, 9, 3, 0, 2 };  
end

  //assign fv = ((a*x*x)-(b*x)+c);

for (i=0; i<10; i=i+1)
begin
  y = x[i];
  always @ (y)
  newpop <= fitf(y,a,b,c);
  assign np[i] = newpop;
end
function automatic integer fitf;     
input [4:0] Y,A,B,C;
begin
  fitf = ((A*Y*Y)-(B*Y)-C);
end
endfunction
endmodule

I am trying to evaluate the function and store values in a array. This is the code i wrote but i get an error in line no 19. please help me out

Upvotes: 0

Views: 115

Answers (2)

Matthew
Matthew

Reputation: 14007

y = x[i]; is a procedural statement. It belongs inside an initial or always block. You have it outside. What's more, y is a reg; you cannot assign to a reg from outside an initial or always block.

Upvotes: 1

Greg
Greg

Reputation: 19122

Generate for-loops are unraveled at compile time. Assignments must be inside a procedural block or assign statement; the begin-end of a generate statement do not count as a procedural block. Therefore y = x[i]; is illegal syntax. reg types must only be updated with in one always block to be synthesize, they cannot be assigned with assign statements in Verilog (okay in SystemVerilog).

Try putting everything onto one always block. 

integer i;
always @* begin
  for (i=0; i<10; i=i+1) begin
    np[i] = fitf(x[i],a,b,c);
  end
end

Upvotes: 2

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