CODEWITHSUNDEEP
moduleverilog
user3195991
user3195991

Reputation: 79

Verilog Error: Must be connected to a structural net expression

I'm getting the error: output or inout port "Qout" must be connected to a structural net expression. I commented the line the error occured in the below code (code is trimmed/condensed). I searched for an answer and it seems I can't assign a input/output port to a reg. I think one solution is to change Q to a wire, but Q is part of an always-block in my eightBitRegister module, so it must be a reg. How can I get around this error?

`timescale 1ns / 1ns

module lab4_3(SW, KEY, LEDR);
    input [9:0] SW;
    input [3:0] KEY; 
    output [7:0] LEDR;

    eightBitRegister eight1(
                .DATA_IN(SW[7:0]),
                .parallelloadn(KEY[1]),
                .rotateRight(KEY[2]),
                .clock(KEY[0]),
                .reset(SW[9]),
                .Q(LEDR[7:0])       
    );      
endmodule

module eightBitRegister(DATA_IN, parallelloadn, rotateRight, reset, clock, Q);
    input [7:0] DATA_IN;
    input parallelloadn;
    input rotateRight;
    input reset;
    input clock;
    output[7:0] Q;


    register reg0(.Qout(Q[0]),  //GETTING ERROR HERE
                .right(Q[1]),
                .left(Q[7]),
                .D(DATA_IN[0]),
                .loadleft(rotateRight),
                .loadn(parallelloadn),
                .clk(clock),
                .rst(reset));

   reg [7:0] Q;
    always @(*)
    begin
     case({parallelloadn,rotateRight})
        2'b00: Q = DATA_IN; 
        2'b01: Q = DATA_IN;  
        2'b11: Q = Q >> 1;
        2'b10: Q = Q << 1;
     endcase
    end

endmodule

module register(Qout, right, left, D, loadleft, loadn, clk, rst);
    input right, left;
    input D;
    wire datato_dff, rotatedata;
    input loadleft, loadn;
    input clk, rst;
    output Qout;

flipflop F0( 
    .d(datato_dff), 
    .q(Qout), 
    .clock(clk),
    .reset(rst) 
);

module flipflop(d, q, reset, clock); 
    input reset, clock;
    input d;
    output q;
    reg q;
    always @(posedge clock)
    begin
        if (reset == 1'b0) 
            q <= 0; 
        else 
            q <= d; 
    end

endmodule

Upvotes: 2

Views: 28829

Answers (1)

sharvil111
sharvil111

Reputation: 4381

First of all, endmodule is missing after flipflop F0 instantiation. Nested modules are not supported by Verilog (This may be a typo error).

Secondly, Qout is driven by multiple drivers. You have driven Qout from .Qout(Q[0]), i.e. from register module, and from always block. This is illegal.

The output of module must be connected to a wire. Even though Qout is an output port, it is used as an input for your logic to drive Q. So, you need to take a wire from register module and use it to drive Q of eightBitRegister module.

Following image shows the port connection rules for input,output and inout ports.

Port Connection Rules

I've modified your code, a bit. Here, a temporary wire is used as workaround. The code is available at EDAPlayground.

Upvotes: 9

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