CODEWITHSUNDEEP
verilogsystem-verilog
射命丸大新文
射命丸大新文

Reputation: 13

Problem with error (vlog-2110) Illegal reference to net

I'm writing a SystemVerilog assignment to simulate a logic circuit, and the following errors occur. I cannot understand how to deal with it. Please help.

These are the error messages:

** Error: E:/ModelSim File/work/1c.sv(8): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(8): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(8): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(10): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(10): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(10): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(12): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(12): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(12): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(14): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(14): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(14): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(16): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(16): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(16): (vlog-2110) Illegal reference to net "C".
** Error: E:/ModelSim File/work/1c.sv(18): (vlog-2110) Illegal reference to net "A".
** Error: E:/ModelSim File/work/1c.sv(18): (vlog-2110) Illegal reference to net "B".
** Error: E:/ModelSim File/work/1c.sv(18): (vlog-2110) Illegal reference to net "C".

this is my code:

module biii (input logic A,B,C,
output logic F);
assign F = ~(~(A & C) & (B & ~(C)));
endmodule

module t_1c(input logic A,B,C,
output logic F);
biii B2(A,B,C,F);

initial begin

#20
A=0;B=0;C=0;
#20
A=0;B=1;C=0;
#20
A=0;B=0;C=1;
#20
A=1;B=1;C=0;
#20
A=1;B=0;C=0;
#20
A=0;B=1;C=0;
#20;
end
endmodule

Upvotes: 1

Views: 240

Answers (1)

toolic
toolic

Reputation: 61937

The t_1c module looks like a testbench. In that case, you do not need to declare the signals as module ports. The errors mean that you cannot make an assignment to a signal declared as an input port inside a module. Change:

module t_1c(input logic A,B,C,
output logic F);

to:

module t_1c;

logic A,B,C,F;

Upvotes: 1

Related Questions