CODEWITHSUNDEEP
verilogsystem-verilog
SSadh
SSadh

Reputation: 91

Error: "(vlog-2110) Illegal reference to net"

I have a simple FIFO code in SystemVerilog. I get several vlog-2110 illegal reference to net error messages. My error messages are followed by my code.

Error messages:

vlog -work work -sv -stats=none C:/Users/Single_FIFO.sv Model Technology ModelSim DE vlog 10.4 Compiler 2014.12 Dec 3 2014 -- Compiling module fifo_core_and_cntl
Error: C:/Users/Single_FIFO.sv(24): (vlog-2110) Illegal reference to net "occucy".
Error: C:/Users/Single_FIFO.sv(26): (vlog-2110) Illegal reference to net "empty".
Error: C:/Users/Single_FIFO.sv(28): (vlog-2110) Illegal reference to net "empty".
Error: C:/Users/Single_FIFO.sv(30): (vlog-2110) Illegal reference to net "full".
Error: C:/Users/Single_FIFO.sv(32): (vlog-2110) Illegal reference to net "full". ...... ......

My simple FIFO code: the small offending portion of it, is shown below.

module fifo_core_and_cntl (data_in, data_put, data_get, clk, reset_n, data_out, occucy, empty, full); 
  input [7:0]data_in;
  input data_put, data_get, clk, reset_n;
  output [7:0]data_out;
  output empty, full;
  output [4:0]occucy;
  logic [4:0]current_readptr, current_writeptr, next_readptr, next_writeptr;
  logic [15:0][7:0]data_fifo;   // This is data Fifo: 2D packed array of vectors: sixteen 8 bit vectors.

  always_ff @ (posedge clk, negedge reset_n) // For the Current counter updates.
    if (!reset_n)
    begin   
      current_writeptr <= 0;
      current_readptr <= 0;
    end
    else
    begin
      current_writeptr <= next_writeptr;    
      current_readptr <= next_readptr;
    end
  end

  always_comb begin  // Combo logic for fifo status outputs and also for internal fifo rd/wr pointer updates.
    occucy = current_writeptr - current_readptr;     // fifo occupancy indication
    if (current_writeptr == current_readptr)
      empty = 1'b1;
    else
      empty = 1'b0;
  end
endmodule

Upvotes: 9

Views: 55230

Answers (2)

dave_59
dave_59

Reputation: 42616

You cannot make procedure assignments to wires, which is the signal kind for your outputs by default. Since you are already using SystemVerilog, you should update your port declaration list to make it much simpler

module fifo_core_and_cntl ( 
  input wire [7:0] data_in,
  input wire data_put, data_get, clk, reset_n,
  output logic [7:0]data_out,
  output logic empty, full,
  output logic [4:0]occupy
);

You should also read this article: https://blogs.sw.siemens.com/verificationhorizons/2013/05/03/wire-vs-reg/

Upvotes: 0

Tudor Timi
Tudor Timi

Reputation: 7573

empty and full are declared as output, which means their implied type is wire. You can only drive wires with a continuous assign:

assign empty = some_value;

If you want to assign these signals from an always block, you should explicitly declare them as logic (or reg if you're using Verilog):

output logic empty, full;

Upvotes: 17

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