CODEWITHSUNDEEP
vhdlhardware
Aboudi
Aboudi

Reputation: 318

Why couldn't I convert this integer into a logic_vector?

I have been trying to convert this Signal of type integer into an std_logic vector and assign the converted value into another signal that has the same width as a VHDL integer 

signal temp : std_LOGIC_VECTOR(31 downto 0) := (others => '0'); 
signal FrameCumulative : integer :=0;

temp <= to_stdlogicvector(to_unsigned(FrameCumulative));

However I get this error:

Error (10346): VHDL error at vga.vhd(107): formal port or parameter "SIZE" must have actual or default value

I am using use IEEE.NUMERIC_STD.ALL; and use IEEE.STD_LOGIC_1164.ALL;

First I made the mistake of not checking the integer size within VHDL and tried to assign an integer into a 14-bit vector but after I gave it some thought I relised my mistake.

Now according to many on-line resources, what I am doing should work but my synthesiser complains about it.

If you do know the cause for this would you mind ellaborating on your answer rather than just posting the correct code, Thanks!

Upvotes: 0

Views: 1393

Answers (1)

scary_jeff
scary_jeff

Reputation: 4374

The function to_unsigned must be provided with a parameter specifying the width of the vector that you want it to produce. The function to_stdlogicvector is also not the correct thing to be using. Your line should look like this:

temp <= std_logic_vector(to_unsigned(FrameCumulative, temp'length));

The function to_unsigned is a conversion function, it must be provided with the target width. Here, as suggested by @BrianDrummond, the width is specified by taking the length attribute from the target vector itself (temp). The std_logic_vector is a type cast, where the unsigned value is simply interpreted directly as an std_logic_vector.

Upvotes: 3

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