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vhdlmodelsim
rkshthrmsh
rkshthrmsh

Reputation: 119

VHDL: Indexing in component port map

    comp_A1: comp_A port map    (   CLK     =>  CLK,
                                    RESET_N =>  RESET_N,
                                    DATA_IN =>  DATA(to_integer(unsigned(count))),
                                    VLD_IN  =>  VLD_IN,
                                    DATA_OUT=>  DATA_OUT,
                                    VLD_OUT =>  VLD_OUT,
                                    BUSY_OUT=>  BUSY_OUT
                                );

In the above snippet I am trying to pass 'DATA' serially to the 'DATA_IN' pin of component comp_A1 within a testbench. 'DATA' and 'count' are both std_logic_vectors. All other signals are std_logic. 'DATA' is a constant vector of size 64 bits and 'count' is a vector being incremented at every rising edge(CLK).

During compilation Model Sim shows me the following errors only,

  1. (vcom-1450) Actual (indexed name) for formal "DATA_IN" is not a static signal name.
  2. VHDL Compiler exiting.

Is the error to do with 'count' being dynamic? What would be a workaround to do this?

Upvotes: 2

Views: 947

Answers (1)

scary_jeff
scary_jeff

Reputation: 4374

Just move the multiplexer created with the line DATA(to_integer(unsigned(count))) to a separate statement using an intermediate signal, for example:

selected_data <= DATA(to_integer(unsigned(count)));

...

DATA_IN => selected_data

Upvotes: 4

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