CODEWITHSUNDEEP
verilog
ragzputin
ragzputin

Reputation: 397

How do you split long lines of code in verilog?

I've just started using Verilog to code FIFO's and other complex logic. I was wondering how to split a long line of code in verilog (similar to say the \ in some languages like C?)

I have the following line of code which is incredibly long -

pushinl = (read_allow&(~pushinl))|(pushinl&read_allow&(~(stopout_a0&stopout_a1&stopout_a2))|(pushinl&read_allow&(stopout_a0&stopout_a1&stopout_a2));

I wasn't able to find any answers online that help with this problem in verilog. Is there a character used in verilog to split the above line?

I am using vi as my main editor. When I write this line of code as it is, I get the following syntax error:

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "fpam2.v", 150: token is ';'
                 |(pushinl&rctrl&(sout_a0&sout_a1&sout_a2));
                                                            ^

1 error
CPU time: .065 seconds to compile

Upvotes: 2

Views: 17314

Answers (1)

Prakash Darji
Prakash Darji

Reputation: 998

You can just give new line to OR(SOP) operator or AND(POS) operator, this gives you more readability and handy debugging. 

pushinl = (read_allow & (~pushinl))
        | (pushinl & read_allow & (~(stopout_a0 & stopout_a1 & stopout_a2))
        | (pushinl & read_allow & (stopout_a0 & stopout_a1 & stopout_a2));

There is no special character of symbol like '\' is used in verilog.

Try this,

pushinl = (read_allow & (~pushinl))
        | (pushinl & read_allow & (~(stopout_a0 & stopout_a1 & stopout_a2)))
        | (pushinl & read_allow & (stopout_a0 & stopout_a1 & stopout_a2));

In second line there is missing of bracket.

Upvotes: 5

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