CODEWITHSUNDEEP
verilogsynthesis
sujeto1
sujeto1

Reputation: 411

What exactly does it means the Argument in the always @ ( ) expression in Verilog?

When I have a sensitivity expression like this:

always @ (data)
begin
.
.
end

does it means that every time "data" change the "begin" process will occur? But what happen if the data actually change to a same number, for instance: reading a list of finite numbers (where value of data sometimes is the same than its contiguous). In this case, would it recognize it as a new data (even though is the same value) or would it just ignore it as a "change" and "begin" won't activate itself?

Upvotes: 2

Views: 1449

Answers (3)

dave_59
dave_59

Reputation: 42698

The other answers are only relevant from an RTL synthesis point of view. For higher levels of synthesis, or from a non-synthesis point of view, it think this is a clear description:

An always construct instantiates a single process that begins at time 0 of a simulation and exists for all time after that. That process may consist of a single procedural statement, or a block of procedural statements. When the procedural statement or statements complete, the process starts the procedural statements over again.

Now, any procedural statement can have a timing control in front of it, like @(expression) or #(delay). The @(expression) means wait for a change in the value of the expression. The change has to come after executing the statement having the timing control. This is why 

always @(data) statement;

does not become an infinite loop.

The reason why the above should not be read as "every time data changes, execute statement" is because if that statement blocked for some about of time while data changed again, the statement does not get executed until after it has completed. For example

always @(posedge clk) do_this;

task do_this;
  // some stuff
  @(posedge clk);
  // some more stuff
endtask

The do_this task does not get called every @(posedge clk). It gets called every other @(posedge clk).

It possible to have 

always @(data) statement;

execute more than once in the same slot, but that depends on both how data changes its value as well as what the statement is, bit I'll leave that for a more advanced discussion.

Upvotes: 2

sharvil111
sharvil111

Reputation: 4381

always@ blocks are used to describe events that should happen under certain conditions.

always@( * ) blocks are used to describe Combinational Logic, or Logic Gates.

always@(posedge Clock) (“always at the positive edge of the clock”) or always@(negedge Clock) (“always at the negative edge of the clock”) blocks are used to describe Sequential Logic, or Registers.

The sensitivity list specifies which signals should trigger the elements inside the always block. The following are some examples:

always @ ( A or B ) begin // executes when A=1 or B=1
// always @ ( * )   begin // same as above. executes when A=1 or B=1
 C = A & B ;
end

always @ ( A and B ) begin // executes when A=1 AND B=1
 C = A & B ;
end

Incomplete sensitivity lists are almost NEVER desired. They introduce very hard-to-find bugs. As such, we use always@(*). ‘*’ sets the sensitivity list to any values that can have an impact on a value(s) determined by the always@(*) block.

In your case, if data remains the same, then always block will never be executed. In your case too, if it is a combinational block, always@(*) is recommended.

If the data remains the same at every time stamp, then the given always block shall not be executed. Since the inputs/sensitivity elements (@(data)) have remained same and outputs/computed elements (logic value computation inside always block) which are computed should also be same.

For somewhat more details, Always block PDF might be useful.

Upvotes: 4

Prakash Darji
Prakash Darji

Reputation: 998

Yes! You are right. Suppose data change on every clock, and data_delayed is flopped version of data, then begin...end is executed only when data_delayed != data, so if data change to same value it won't be executed.

Upvotes: 2

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