CODEWITHSUNDEEP
vhdl
user3026388
user3026388

Reputation: 300

VHDL code error

I have this code for a Serial Adder in VHDL. I am trying to get it to work, but I keep on getting an error that says:

Errors found in VHDL File -

Line : 17, Error : Index constraint expected in the subtype indication

This error is referring to the line:

signal state, next_state : integer range 0 to 3;

I'm not sure why this is happening. Any help? Please find the full code below.

library ieee;
use ieee.std_logic_1164.all;

entity adder is
 port(
 start : in std_logic;
 clk : in std_logic;
 a_out : out std_logic_vector(3 downto 0)
 );
end adder;

architecture behave of adder is
signal a, b : std_logic_vector(3 downto 0);
signal shift : std_logic;
signal Cin, Cout : std_logic;
signal sum_in : std_logic;
signal state, next_state : integer range 0 to 3;

begin
 sum_in <= a(0) xor b(0) xor Cin;
 Cout <= (Cin and a(0))or(Cin and b(0))or(a(0) and b(0));
 a_out <= a;

 process(state, start)
 begin
  case state is
   when 0 =>
   if start = '1' then shift <= '1'; next_state <= 1;
   else shift <= '0'; next_state <= 2; end if;
    when 1 => shift <= '1'; next_state <= 2;
    when 2 => shift <= '1'; next_state <= 3;
    when 3 => shift <= '1'; next_state <= 0;
   end case;

 end process;

 process(clk)
 begin
  if clk'event and clk = '0' then
   state <= next_state;
   if shift = '1' then
    a <= sum_in & a(3 downto 1);
    b <= b(0) & b(3 downto 1);
    Cin <= Cout;
   end if;
  end if;

 end process;

end behave;

Upvotes: 2

Views: 766

Answers (1)

Kartik Agarwal
Kartik Agarwal

Reputation: 1403

Try to replace your line in which you are getting error by:
signal state, next_state : integer is range 0 to 3;

If you are specifying range then you should use is range instead of range

Upvotes: 0

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