CODEWITHSUNDEEP
logicoperatorsverilog
newb7777
newb7777

Reputation: 563

Verilog 5 ways of defining the same logic, Is there any difference between the 5 codes

All the codes are in the pictures ands my question is that if the codes will give me different results. I am especially doubtful about the differences between method 3 and 3b and for the convenience, I have outlined it below. Between 3 and 3b, one uses the assign statement for XOR and the other uses straight up XOR. 1) Since it is outside the always @ posedge of clock statement, will it still execute similar to one another? 2) I am certain, and I read it somewhere that assign runs continuously.. Does the combinatorial logic (xor U1(Z.....) need to be placed in a "always @ (*)" block so it would run similar fashion as the assign statement?

xor U1(Z,A,D);//uncomment this line for METHOD 3
assign Z=A^D; //uncomment this line for METHOD 3b

The full code......

 module SetupHold(
 input wire clock,
input wire B,
input wire C,
input wire E,
input wire F,
input wire H,
input wire J,
output reg K
);

reg A,D,G;
//wire Z;//uncomment this line for METHOD 3 & 3b

//xor U1(Z,A,D);//uncomment this line for METHOD 3
//assign Z=A^D; //uncomment this line for METHOD 3b

always@(posedge clock) begin
A <= B ^ C;
D <= E & F;
G <= H | J;
//K <= G ? ~&{A,D} : ^{A^D};//uncomment this line for METHOD 1
//K <= G ? ~&{A,D} : (A^D); //uncomment this line for METHOD 2
//K <= G ? ~&{A,D} : Z;//uncomment this line for METHOD 3 &3b
if (G==1)//uncomment this line for METHOD 4
     K<=~&{A,D};//uncomment this line for METHOD 4
else //uncomment this line for METHOD 4
     K<=(A^D);//uncomment this line for METHOD 4
end
endmodule

Method1

Method2

Method3

Method3b

Method4

Upvotes: 0

Views: 70

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

For Verilog as a Hardware Description Language (HDL), the 5 different implementations of the same logical function will result in equivalent hardware if given to a synthesis tool. So logical operation of the hardware will be the same.

But note that synthesis tools have a lot of freedom in choosing the specific implementation based on for example timing constrains and device filling, so you may see differences in implementations from run to tun when looking at the gate representation. The implemented logical function will however be equivalent.

Upvotes: 1

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