CODEWITHSUNDEEP
verilogxilinx-ise
user2286339
user2286339

Reputation: 194

ModelSim SE 5.7: unexpected 'Z' and 'X'

While getting my feet wet with an old Spartan2-Board I tried to setup a 1-bit full adder with the Verilog code and accompanying testbench as below:

module full_adder(s, cout, a, b, cin);
output s, cout;
input a, b, cin;

wire t1, t2, t3;

xor (t1, a, b);
xor (s, t1, cin);
and (t2, t1, cin);
and (t3, a, b);
or  (cout, t2, t3);
endmodule

Testbench:

module tb_full_adder;

// Inputs
reg a;
reg b;
reg cin;

// Outputs
wire s;
wire cout;

// Instantiate the Unit Under Test (UUT)
full_adder uut (
    .s(s), 
    .cout(cout), 
    .a(a), 
    .b(b), 
    .cin(cin)
);

initial begin
    // Initialize Inputs
    a = 0;
    b = 0;
    cin = 0;

    // Wait 100 ns for global reset to finish
    #100;

    //125 ns
    #25;    a = 1'b1;
    //150 ns
    #25;    a = 1'b0;   b = 1'b1;
    //175 ns
    #25;    b = 1'b0;   cin = 1'b1;

end      
endmodule

I had to use ISE 10.1 and ModelSim SE 5.7 because the more recent versions of the ISE don't support any of the Spartan devices any more, IIUC (let alone Vivado). The issue is that the 'Wave window' of ModelSim shows all the signals as either hi-Z or don't care 'X':

ModelSim SE 5.7 trace window

If I setup the exact same project in ISE 14.7, the code also compiles and the simulation, in this case it's the more recent ISim, shows the expected traces:

ISim (ISE 14.7)

What is the difference between ModelSim and ISim, besides its age ? What am I missing ?

best, Chris

Upvotes: 0

Views: 2468

Answers (1)

Matthew
Matthew

Reputation: 13967

There is nothing different between Modelsim and ISim in this respect. With Modelsim you have not simulated your testbench. I can tell that because the signal names in the waveform viewer all start /full_adder/ rather than /tb_full_adder/uut/. I manged to get a similar waveform to your ISim waveform in Modelsim by simulating the testbench, too, ie by typing vsim tb_full_adder in the transcript window.

Upvotes: 1

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