CODEWITHSUNDEEP
verilogmodelsim
Baum
Baum

Reputation: 35

ModelSim unexpected z input

I'm building a simple 7-segment display. I didn't have errors when I was compiling the module and testbench. But, when I'm simulating, I keep getting z value as input. Why do I get the z?

Verilog code as below :

module  dec_7seg(d, seg);

input [3:0]d;
output [7:0]seg;

assign seg[1]= (d[1]&~d[2]) | d[0] | (~d[1]&d[2]) | (d[2]&~d[3]);
assign seg[2]= (~d[0]&d[1]) | (~d[1]&~d[2]&~d[3]) | (d[1]&d[2]) | (d[0]&~d[1]&d[3]);
assign seg[3]= (~d[1]&~d[3]) | (d[0]&d[1]) | (d[2]&~d[3]) | (d[0]&d[2]);
assign seg[4]= (~d[1]&~d[3]) | (d[1]&~d[2]&d[3]) | (~d[1]&d[2]) | (d[2]&~d[3]) | (d[0]&~d[3]);
assign seg[5]= (~d[2]&d[3]) | (~d[0]&d[1]) | (~d[0]&~d[2]) | (d[0]&~d[1]) | (~d[0]&d[3]);
assign seg[6]= (~d[1]&~d[2]) | (~d[0]&~d[2]&~d[3]) | (~d[0]&~d[1]) | (~d[0]&d[2]&d[3]) | (d[0]&~d[2]&d[3]) | (d[0]&d[2]&~d[3]);
assign seg[7]= (~d[1]&~d[3]) | (~d[0]&d[2]) | (d[1]&d[2]) | (~d[0]&d[1]&d[3]) | (d[0]&~d[1]&~d[2]);

endmodule

Testbench :

  `timescale 1ns/1ps
module tb_dec_7seg_selfchecking();
reg [3:0] d;
wire [7:0] seg;
dec_7seg U0(.d(d),.seg(seg));

initial begin
d=4'b0000; #10; //0000
if(seg !== 8'b11111100)$display("0 fail");
d=4'b1000; #10; //0001 
if(seg !== 8'b01100000)$display("1 fail");
d=4'b0100; #10; //0010
if(seg !== 8'b11011010)$display("2 fail");
d=4'b1100; #10; //0011
if(seg !== 8'b11110010)$display("3 fail");
d=4'b0010; #10; //0100
if(seg !== 8'b01100110)$display("4 fail");
d=4'b1010; #10; //0101
if(seg !== 8'b10110110)$display("5 fail");
d=4'b0110; #10; //0110
if(seg !== 8'b10111110)$display("6 fail");
d=4'b1110; #10; //0111
if(seg !== 8'b11100100)$display("7 fail");
d=4'b0001; #10; //1000
if(seg !== 8'b11111110)$display("8 fail");
d=4'b1001; #10; //1001
if(seg !== 8'b11100110)$display("9 fail");
d=4'b0101; #10; //1010
if(seg !== 8'b11111010)$display("a fail");
d=4'b1101; #10; //1011
if(seg !== 8'b00111110)$display("b fail");
d=4'b0011; #10; //1100
if(seg !== 8'b00011010)$display("c fail");
d=4'b1011; #10; //1101
if(seg !== 8'b01111010)$display("d fail");
d=4'b0111; #10; //1110
if(seg !== 8'b11011110)$display("e fail");
d=4'b1111; #10; //1111
if(seg !== 8'b10001110)$display("f fail");


end
endmodule

Upvotes: 1

Views: 764

Answers (1)

toolic
toolic

Reputation: 62064

You do not drive seg[0]. An output port is implicitly declared as type wire, and wire types default to z when undriven. To get rid of the z, since your testbench expects bit 0 to be 0, you could add this line inside your dec_7seg module:

assign seg[0]= 0;

Upvotes: 1

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