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optimizationverilogmodelsim
Saad Riaz
Saad Riaz

Reputation: 3

Modelsim Optimization Issue

I am having problem when I am trying to run the following verilog code snippet in Optimized mode using Modelsim simulator v10.2c.

always @ *
  if (dut.rtl_module.enable == 1'b1)
    force dut.rtl_module.abc_reg = xyz;

If the above snippet is run in non-optimized mode, this works fine. But for optimized mode, it fails.

PS: I am using -O5 optimization level

Upvotes: 0

Views: 3730

Answers (1)

Chiggs
Chiggs

Reputation: 2864

Optimisation typically disables access to simulator objects. Your force command requires that access.

You'll need to explicitly enable access. Unfortunately I can't see anything useful in the Modelsim AE documentation, however from Riviera-PRO:

 +accs
         Enables access to design structure. This is the default in -O0,
         -O1 and -O2 and may optionally be specified for -O3. If omitted,
         the compiler may limit read access to selected objects.

Modelsim supports +acc, it just doesn't appear to be well documented. The only reference appears to be this suggestion:

While optimization is not necessary for class based debugging, you might want to use 
vsim -voptargs=+acc=lprn to enable visibility into your design for RTL debugging.

Upvotes: 2

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