CODEWITHSUNDEEP
vhdlxilinx-ise
maryam
maryam

Reputation: 23

An error in VHDL code in Xilinx ISE

I am trying to write a 1-bit comparator VHDL code in Xilinx ISE.

There are no errors in the code but when I tried to create a schematic symbol, this error has arisen:

ERROR: G:/eq/eq.sym was not updated. Set the 'Overwrite Existing Symbol' process property to enable overwritting of existing symbol files.

What can I do to fix this problem? 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity eq is
  port (
    i0 : in  STD_LOGIC;
    i1 : in  STD_LOGIC;
    eq : out STD_LOGIC);
end eq;

architecture sop_arch of eq is
  signal P0 , p1: std_logic;
begin
  eq <= P0 or p1;
  p0 <= ( not i0) and ( not i1);
  p1 <= i0 and i1;
end sop_arch;

Upvotes: 0

Views: 1078

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