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processcasevhdlclockperiod
Gabriel
Gabriel

Reputation: 1

Time division (Period) Selection in vhdl

I am currently doing a project in VHDL in which I have a counter that needs to be updated in 100ms or in 1000 ms if a Key is pressed.

Example:

If Key3=0 then
 c=c+1 (100ms)
elsif key3=1 then
 c=c+1 (1000ms)

I'd like to know how to do it in VHDL.

I Believe I should use a process(clock, Key3) but I am not sure how to make the counter increase based on the period.

thanks in advance !

Upvotes: 0

Views: 1329

Answers (2)

user1818839
user1818839

Reputation:

If c is a variable (in a process) of type time then

if some_condition then 
   c := c + 100 ms;
else
   c := c + 1000 ms;
end if;

is valid VHDL, and will work in simulation, though time is not very well supported for synthesis.

The easiest solution is for C to count in time steps - such as multiples of clock cycles, and to add 1 or 10 of these.

For example if you have a 10MHz clock:

constant Clock_Period : time := 100 ns;

constant ms_100 : natural := 100 ms / Clock_Period;
constant ms_1000 : natural := 1000 ms / Clock_Period;
signal c : natural;
...

    if some_condition then 
       c <= c + ms_100;
    else
       c := c + ms_1000;
    end if;

And if you change the clock frequency, adjust the clock_period declaration to match.

Upvotes: 1

PlayDough
PlayDough

Reputation: 1138

I think you are part way there:

I Believe I should use a process(clock, Key3) but I am not sure how to make the counter increase based on the period.

Think of the problem as a digital design problem, not a coding problem. What would you use to measure the passage of time with in a real digital system? From there use that as a reference to determine whether 100ms or 1000ms have passed.

And once you can measure time, how do you determine how long a particular event is in process?

Upvotes: 1

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