CODEWITHSUNDEEP
vhdl
AKage
AKage

Reputation: 11

Illegal Concurrent Statement in VHDL?

I've been trying to learn how to use conditional signal assignments in VHDL (which are the WHEN ELSE statements I believe?) and came up with what SHOULD be a simple code. But ModelSim doesn't let it compile and keeps telling me that I have an illegal concurrent statement. Where? Why? I've tried doing an IF ELSIF ELSE statement inside a process but I still got the exact same error so I'm now more confused than when I started...

Library ieee;
Use ieee.std_logic_1164.all;

Entity Q59122 is port (
    A, B : IN  STD_LOGIC;
    Y    : OUT STD_LOGIC
);
End Entity Q59122;

ARCHITECTURE csa OF Q59122 IS
BEGIN
    Y <= '0' WHEN A = '0'
    ELSE Y <= '0' WHEN B = '0'
    ELSE Y <= '1';
END csa;

Basically I'm trying to imitate an AND gate using conditional signal assignments. I know that there is an "and" command you can use in VHDL but that would defeat the purpose. Thanks for the help in advance.

Upvotes: 1

Views: 17787

Answers (1)

Bill Lynch
Bill Lynch

Reputation: 81936

The concurrent assignment statement should be written as:

Y <= '0' when A = '0' else 
     '0' when B = '0' else
     '1';

If you wanted to use an if-else chain, you would write:

process (A, B)
begin
    if A = '0' then
        Y <= '0';
    elsif B = '0' then
        Y <= '0';
    else
        Y <= '1';
    end if;
end process;

Upvotes: 5

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