CODEWITHSUNDEEP
verilogvivado
mpyro
mpyro

Reputation: 1

How to use verilog to blink an led

I have been trying to make a blinking led in Verilog using vivado. I have a 100MHz FPGA. My code is posted below:

module Blinky(
input clk,
input reset,
output reg led
);


reg [26:0] count; 
wire state;
assign state = count[26];

always@ (posedge clk or posedge reset)
 begin
  if (reset)
   count <= 0;  
  else
   count <= count + 1;  //otherwise increment the register
  end

always@ (posedge state)
    if (led == 1'b1)
        led = 1'b0;
    else
        led = 1'b1;

endmodule

in this code I am attempting to use a clock divider to slow down the clock. I then used the slowed clock signal to switch the led on and off. I know the constraints are correct because I can hard-code the led to go on and off. But when I try this or variations of it nothing happens. Can anyone help?

Upvotes: -1

Views: 2313

Answers (1)

user149341
user149341

Reputation:

You're overcomplicating things. The topmost bit of the counter can be used to drive the LED directly; you don't need to use it as a clock to a separate flip-flop. (Generally speaking, you should use as few separate clock signals as possible in FPGA designs; the FPGA routing fabric only supports a small number of global clocks.)

Change output reg led to output led, remove state and everything referencing it (including the entirety of the second always block), and add:

assign led = count[26];

Upvotes: 0

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