CODEWITHSUNDEEP
verilogsystem-verilog
nikhil0505
nikhil0505

Reputation: 31

array of buffers in verilog

I'm attempting to implement an array of buffers in Verilog where data will ripple through the buffers upon a positive edge of a clock signal (CLK) while an input signal (data_valid) is active. However, I'm encountering a problem where my data_in wire isn't connecting to the first buffer, resulting in my output being stuck in a high-impedance state.

module convolution_ip(input [7:0] data_in, 
                      input reset, input wire init_valid,  clk, 
                       output [9:0] final_output );
                       
    integer j ;
    reg [7:0] input_fm_buff[24:0] ;
    wire input_load;  

    /////////////////////////////////////////
    assign input_load = clk & init_valid;
    /////////////////////////////////////////

    always@(posedge input_load or posedge reset)begin
     if (reset) begin
            // Reset buffer
            for (int j = 0; j <=24; j = j + 1) begin
                input_fm_buff[j] <= 8'h00;
            end
        end else begin
            for (int j = 0; j<=24; j = j+1) begin
               if (j==24)begin  input_fm_buff[j] <= data_in;
               end  
                input_fm_buff[j] <= input_fm_buff[j+1];
            end  
           end
    end
    assign final_output = input_fm_buff[1];
endmodule

schematic is looking like this Schematics

I tried for loop and nonblocking assignments to synchronize the data flow through each buffer. I want the data to ripple through the buffers when init_valid is HIGH and there is a positive edge of a clk.

Upvotes: 1

Views: 314

Answers (1)

Im Groot
Im Groot

Reputation: 647

I see a couple of issues here (apart from your question):

  1. You should use posedge input_load in sensitivity list because this way you are trying to feed clock to your logic via an AND gate. It is not recommended in FPGA because clock routes are different than the data routes i.e. clock signal travels on separate dedicates routes. With the AND gate you are bringing the CLK signal on to normal data routes. So the simple solution is you should use an extra else if in the always block.
  2. Your output should be 8-bit i.e. output [7:0] final_output but you have defined it as 10-bit.

Now, to the main issue of as to why data_in wire isn't connecting to the first buffer? You have defined your logic in the else block, as below, in a way that if j==24 then the if statement is correct and your value get assigned to the buffer address 24 i.e. input_fm_buff[24] <= data_i. But then, followed by the if statement, you are reassigning a new value to input_fm_buff[j] outside the if statement and that happens to be input_fm_buff[j+1], i.e. 25, which is a non-existing memory.

In other words, when j==24 then both the statements input_fm_buff[j] <= data_in; and input_fm_buff[j] <= input_fm_buff[j+1]; are executed, resulting in the implementation of later i.e. input_fm_buff[j] <= input_fm_buff[j+1];.

if (j==24)begin  
    input_fm_buff[j] <= data_in;
end  
    input_fm_buff[j] <= input_fm_buff[j+1];

The solution is to wrap your logic in if else statement.

if (j==24)begin  
    input_fm_buff[j] <= data_in;
end  
else begin
    input_fm_buff[j] <= input_fm_buff[j+1];
end

Upvotes: 0

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