CODEWITHSUNDEEP
verilog
nikhil0505
nikhil0505

Reputation: 31

Issue with Buffers for Input Feature Maps and Neural Network Weights

I'm working on a Verilog implementation involving two arrays of buffers, one for input feature maps and the other for neural network weights. My goal is to ripple data through these buffers when input_valid and weight_valid signals are asserted. However, I'm facing an issue where only the weight buffers seem to be implemented correctly in hardware, while the input_fm_buffers are not functioning as expected. I'm using a for loop and nonblocking assignments to synchronize the data flow from the buffers when valid signals are high. Any insights into why this might be happening?

module convolution_ip(input [7:0] data_in , [7:0]weight_in , 
                      input reset , init_valid,  clk, weight_valid , 
                       output [7:0] final_output );
                       
integer i , j ;

reg [7:0] input_fm_buff[24:0] ;
reg [7:0] weight_buff[24:0]; 

always@(posedge clk or posedge reset)begin
     if (reset) begin
            for (int j = 0; j < 25; j = j + 1)
                 begin
                 input_fm_buff[j] <= 8'h00;
                 weight_buff[j] <= 8'h00;
                 end
        end 
     else 
        begin
        if(init_valid)
            begin
                for (int j = 0; j<25; j = j+1) begin
                     if (j==24)begin  input_fm_buff[j] <= data_in;
                      end 
                     else begin 
                      input_fm_buff[j] <= input_fm_buff[j+1];
                     end
                 end 
           end
        if(weight_valid)begin
            for (int i = 0; i<25; i = i+1) begin
                    if (i==24)begin weight_buff[i] <= weight_in;
                          end 
                    else begin 
                     weight_buff[i] <= weight_buff[i+1];
                    end
             end 
         end 
      end         
end

assign final_output = weight_buff[1];

endmodule

schematic

I've observed something. When I connect the final output to the input_fm, it seems that only the input_fm_buff gets implemented, while the weight_buff remains unaffected. what does this mean?

Upvotes: 0

Views: 39

Answers (1)

Im Groot
Im Groot

Reputation: 647

The input_fm_buff has been optimized out during the synthesis, because it has not been used anywhere in deriving the output logic. weight_buff is implemented correctly because you are deriving the final_output with it as below:

assign final_output = weight_buff[1];

If I remember neural networks correctly, then I think you missed the part where you multiply the weights with the data as below, but you may have different plans. That just an indication. It can be any other operation or something. Multiplication is an example (for multiplication your final_output data width will also change as a result).

assign final_output = weight_buff[1] * input_fm_buff[1];

Secondly about:

I've observed something. When I connect the final output to the input_fm, it seems that only the input_fm_buff gets implemented, while the weight_buff remains unaffected. what does this mean?

I found this incorrect.

When I elaborate design with assign final_output = weight_buff[1], I get this schematics Weight Buffer

When I elaborate design with assign final_output = input_fm_buff[1], I get this schematics Data Buffer

And when I open elaborate design with assign final_output = input_fm_buff[1] + weight_buff[1] (as an example), I get this schematics Combined input side Combined output side

Upvotes: 0

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