CODEWITHSUNDEEP
structtypedefsystem-verilog
miles.sherman
miles.sherman

Reputation: 171

Find largest bit width of synthesizeable data types in systemverilog

I have a number of user-defined data types (all packed structs). I would like to determine the bit-width of the largest of these data types and create a flat array of this size.

My first attempt was to use a union and find its size. However, I am compiling for an Altera FPGA and Quartus does not support SystemVerilog unions. What other options do I have for doing this programatically? My union code which doesn't compile in Quartus is shown below.

typedef logic [7:0] uint8_t;
typedef logic [15:0] uint16_t;
typedef logic [31:0] uint32_t;
typedef logic [63:0] uint64_t;

typedef struct packed
{
    uint8_t field_1;
    uint16_t field_2;
} struct_1_t;

typedef struct packed
{
    uint8_t field_1;
    uint16_t field_2;
    uint32_t field_3;
} struct_2_t;

typedef struct packed
{
    uint8_t field_1;
    uint16_t field_2;
    uint32_t field_3;
    uint64_t field_4;
} struct_3_t;

typedef union
{
    struct_1_t struct_1;
    struct_2_t struct_2;
    struct_3_t struct_3;
} all_structs_t;

localparam MAX_STRUCT_SIZE = $bits(all_structs_t);
logic [MAX_STRUCT_SIZE-1:0] the_buffer;

Upvotes: 0

Views: 611

Answers (1)

dave_59
dave_59

Reputation: 42623

SystemVerilog does not specify the layout of unpacked unions, so what you wrote would not give you what you expect even if synthesis tools supported it.

What you can do is create a MAX function.

function int MAX(int X, Y);
 return (X> Y) ? X : Y;
endfunction
localparam MAX_STRUCT_SIZE = MAX($bits(struct_1_t), MAX($bits(struct_1_t),$bits(struct_1_t)));

Upvotes: 1

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