CODEWITHSUNDEEP
vhdlflip-flop
levshkatov
levshkatov

Reputation: 487

Different flipflops - different outputs for one reset input

I have 9 flipflops and one reset input. I need to set outputs of 8 flipflops to 0 when reset is 0. And output of one flipflop to 1. This flipflop unique and never changed. How to do it?

Code of flipflops:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity d_ff is
   port
   (
      clk : in std_logic;
      rst : in std_logic;     
      d : in std_logic;
      q : out std_logic
   );
end entity d_ff;

architecture logicFunc of d_ff is
begin
   process (clk) is
   begin
        if (rst='0') then   
            q <= '0';
        elsif (clk'event and clk = '1') then 
            q <= d; 
        end if;
   end process;
end architecture logicFunc;

Now this code sets all flipflops to 0 when reset is 0 and I can't change output of first flipflop in main program

Upvotes: 0

Views: 109

Answers (3)

Matthew
Matthew

Reputation: 14007

Why have a d_ff entity at all? Why have a separate level of hierarchy? No professional user of VHDL would do that unless there were some special reason for it. Instead, just implement your 9 flip-flops as a process:

   process (clk) is
   begin
        if rst='0' then   
            q < = "000000001";
        elsif rising_edge(clk) then 
            q <= d; 
        end if;
   end process;

Upvotes: 2

PlayDough
PlayDough

Reputation: 1138

An alternative is to make use of generics. This allows you to use the exact same code for all your d_ff instances. For example:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity d_ff is
   generic
   (
      RESET_VALUE : std_logic
   );
   port
   (
      clk : in std_logic;
      rst : in std_logic;     
      d : in std_logic;
      q : out std_logic
   );
end entity d_ff;

architecture logicFunc of d_ff is
begin
   process (clk) is
   begin
        if (rst='0') then   
            q <= RESET_VALUE;
        elsif (clk'event and clk = '1') then 
            q <= d; 
        end if;
   end process;
end architecture logicFunc;

Then when you make use of it to create your 8 FF's that reset to a '0' and 1 FF that resets to a '1':

library ieee;
use ieee.std_logic_1164.all;

entity foo is
  port map
  (
    clk : in std_logic;
    rst : in std_logic;
    d   : in std_logic_vector(8 downto 0);
    q   : out std_logic_vector(8 downto 0)
  )
end entity foo;

architecture structural of foo is
begin
  ff_gen : for i in 0 to 7 generate
  begin
    ff : entity work.d_ff
    generic map
    (
      RESET_VALUE => '0'
    )
    port map
    (
      clk => clk,
      rst => rst,
      d   => d(i),
      q   => q(i)
    );
  end generate ff_gen;

  ff0_gen : entity work.d_ff
  generic map
  (
    RESET_VALUE => '1'
  )
  port map
  (
    clk => clk,
    rst => rst,
    d   => d(8),
    q   => q(8)
  );
end architecture structural;

Upvotes: 3

Renato
Renato

Reputation: 190

The 8 flip-flops which reset to '0' you can use the code you presented. For the other flip-flop you can create another entity d_ff1:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity d_ff1 is
   port
   (
      clk : in std_logic;
      rst : in std_logic;     
      d : in std_logic;
      q : out std_logic
   );
end entity d_ff1;

architecture logicFunc of d_ff1 is
begin
   process (clk) is
   begin
        if (rst='0') then   
            q <= '1';
        elsif (clk'event and clk = '1') then 
            q <= d; 
        end if;
   end process;
end architecture logicFunc;

This way is in keeping with the way you wanted to have a separate flip-flop entities.

Upvotes: 1

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