CODEWITHSUNDEEP
vhdl
M0o0o0d
M0o0o0d

Reputation: 1

How to specify these conditions in my counter

I had a problem with synthesizing my code with using ISE. Please check the code and give me a suggestion how to modify it with need of a specific condition. My problem is only with the STAYCOUNT entity of a counter. Note that clk is feeding by another circuit and staycount is also feeding by another circuits.

  1. at the initialization step, STAYCOUNT = 0, and if Reset = 0 , and the clk = 1 then count=count+1, and give an output DOUT = COUNT.
  2. if reset = 1 then count = count - count.
  3. then the next circuit process the output of DOUT, and it will either stop feeding the counter or feeding it (staycount = 1) in a specific condition.
  4. whenever staycount = 1. if clk = 1 then while staycount = 1 loop count = count + 1 DOUT <= count end loop
  5. end if

there are 2 problems: 1. at the initialization step only if staycount = 0 and clk= 1 it should only process count=count+ 1 for only 1 time and give an output DOUT. After DOUT send a signal to another circuit, this circuit has 2 output either staycount which is going to be equal to 1 or proceed to for another output. 2. suppose that the other circuit give an output staycount = 1, it should feed the counter, and the counter again will check if the clk= 1 and the staycount= 1 to make count=count + 1 and give another output DOUT = COUNT.

please check my code for the counter. However, it missed the statement of problem#1, and succeeded in problem# 2, but with error Xilinx ISE "Non-static loop limit exceeded".

entity counter is

    generic(n: natural :=4);
    port(   CLK: in std_logic;
            Reset : in std_logic;
            staycount: in std_logic;
            DOUT    : out   std_logic_vector(n-1  downto 0) );
end counter;

architecture behavior of counter is

begin 

    process(CLK,CLK,Reset,staycount,COUNT) -- behavior describe the counter
    variable COUNT:std_logic_vector(n-1  downto 0); 
        begin

           if Reset = '1' then
              COUNT := COUNT - COUNT;

              elsif (CLK='1' and CLK'event) then
            while (staycount = '1') loop
            COUNT := COUNT + 1;
                DOUT <= COUNT after 50 ns;
                end loop;   
          else DOUT <= COUNT;
          end if;               

    end process;
end behavior;

Upvotes: 0

Views: 971

Answers (1)

Casperrw
Casperrw

Reputation: 531

Make count a register

It looks like you are using count to keep the state of your design. It is neater, and often easier to debug, to make it a signal - which becomes a register if you assign it on clock edges.

Declare count as a signal in the architecture instead of as a variable, and assign it its next value at every clock edge. I also recommend resetting, in the process, to zeros instead of subtracting by itself - otherwise you may end up with propagating uninitialized values in your implementation.

if reset = '1' then
    count <= (others => '0');
elsif (CLK='1' and CLK'event) then
    count <= count_n;
end if;

Assign the count_n signal concurrently, being mindful of that you always want to increment it at least once:

count_n <= (n-1 downto 1 => '0') & '1' when count = 0 else
           count when staycount = '0' else 
           count + 1;

Now also assign your output concurrently based on the count signal, and note that you can limit your sensitivity list to only clk and reset.

Upvotes: 0

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