CODEWITHSUNDEEP
verilogsystem-verilog
Hemant Bhargava
Hemant Bhargava

Reputation: 3585

Verilog concatenation of decimal and string literal

I want to concatenate decimal with the string. Like:

parameter AWIDTH = 15;
...
...

wire [AWIDTH-1:0] addra_bus;
assign addra_bus = cg_one ? {addra} : {AWIDTH, "'bz"};

On basic of 'cg_one', it would pick either {addra} or {AWIDTH, "'bz"}. In false condition of ternary operator I am concatenating AWIDTH with 'bz. If cg_one is 1'b0, I should get 15'bz as value in addra_bus. Make sense?

Problem is while synthesizing this code. I get a warning as :

WARNING: expression size 56 truncated to fit in target size 15 (VERI-1209)

Why is it so? From where size 56 is coming?

Upvotes: 0

Views: 1903

Answers (3)

Rahul Menon
Rahul Menon

Reputation: 792

As Dave already mentioned to put the bus to high state you could do assign addra_bus = cg_one ? addra : {AWIDTH{1'bz}}; But setting a bus to "z" in a synthesizable code is not desired until you are driving a chip-level IO signal.

If you want to display the string 15'bz in the bus for debug .

reg [7:0]  val = {"0"+AWIDTH%10};
reg [7:0]  val1 = {("0"+AWIDTH/10)};
assign addra_bus = cg_one ? {addra} : {val,val1};

[ assuming you param size is only unto 99.][ as you need 8 bits per character the code above only displays "15" ]

Upvotes: 0

Tomáš Kratochvíla
Tomáš Kratochvíla

Reputation: 763

Your are trying to save by default 32 bit AWIDTH and 24 bit "'bz" (56 bits in total) into 15 bit addra_bus.

You should limit the width of the AWIDTH and increase the width of addra_bus . For example:

parameter AWIDTH = 6'd30;

wire [AWIDTH-1:0] addra_bus;
assign addra_bus = cg_one ? {addra} : {AWIDTH, "'bz"};

Upvotes: 1

dave_59
dave_59

Reputation: 42788

You should not be using a string literal. All you need to do is

assign addra_bus = cg_one ? addra : 'z;

'z will be expanded to the width of addra_bus

Upvotes: 3

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