CODEWITHSUNDEEP
verilogsystem-verilog
user849204
user849204

Reputation:

single quote in front of bit concatenation in verilog

logic[1:0] a;
logic[1:0] b;
assign a = {1'b0, 1'b1};
assign b = '{1'b0, 1'b0};

Is there a difference between having ' in front of {} in Verilog/SystemVerilog?

Upvotes: 4

Views: 4348

Answers (1)

dave_59
dave_59

Reputation: 42673

Yes. As soon as you put the ' in front, you no longer have a concatenation; you have an assignment pattern. There are many cases where the result looks the same, but the main difference is in a concatenation, each operand is evaluated in a self-determined context, and in an assignment pattern, each operand is in a context of an assignment to each element in the pattern. Take this modified example:

assign a = {2'b1,2'b0}; // result is 4'b0100, a == 2'b00
assign b = '{2'b1,2'b0}; // result is b[1] = 2'b1, b[0] = 2'b0; b == 2'b10

The width of the concatenation is 4-bits and gets truncated to 2-bits. In the assignment pattern, each operand gets truncated from 2 to 1 bits.

Concatenations have other features not available in an assignment pattern, like replication a = {2{1'b1}}; Assignment patterns have features not available in concatenations, like index labeling b = '{0:1, 1:0}; b = 2'b01. This feature becomes very useful in structures and associative arrays. For example

string AA[int] = '{0:"zero", 1:"one",2:"two",default:"undefined"};

AA[0], AA[1], and AA[2] return "zero", "one", and "two" respectively. But any other index returns the string "undefined"

Upvotes: 9

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