CODEWITHSUNDEEP
concatenationverilogbit
user1763658
user1763658

Reputation: 35

Concatenation operator not allow in module instantiation

MUX32_16x1 inst9(muxR, dontNeed, addSub, AddSub, mult, shift, shift, wireAnd, wireOr, wireNor, {31{0}, addSub[31]}, dontNeed, dontNeed, dontNeed, dontNeed, dontNeed, dontNeed, OPRN[3:0]);

Above is my instantiation of a 16x1 mux, I'm trying to set one parameter to 0 for the first 31 bits leaving only the last bit as an input by doing this 

{31{0}, addSub[31]}

I'm not sure why the program is giving out this error

near ",": syntax error, unexpected ',', expecting '}'.

is curly braces operator not allow in module instantiation?

sorry, I'm very new to Verilog programming

Upvotes: 0

Views: 878

Answers (1)

Charles Clayton
Charles Clayton

Reputation: 17946

When you're doing repeated concatenation, you need to enclose it in another set of braces, so {31{1'b0}} is the same as 31'd0.

Try: 

{{31{1'b0}}, addSub[31]}

Or:

{31'd0, addSub[31]}

Upvotes: 1

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