How do I fix this error: System verilog keyword 'bit' is not expected to be used in this context?

Question

I'm getting the following error:

 Parsing design file '../src/divi .v '
 Error-[SE] Syntax error    " Following verilog source has syntax error
 
 **.../src/divi .v", 12: token is 'bit' reg [4:0]   bit;**
 
 System verilog keyword 'bit'is not expected to be used in this
 context.  
 1 error CPU time: .143 seconds to compile eng-svr0:/class/linux/avicente/ASIC_Design/work>

Code:

module streamlined_divider(quotient,remainder,ready,dividend,divider,start,clk);


input [15:0]  dividend,divider;
   input         start, clk;
   output [15:0] quotient,remainder;
   output        ready;
   
   reg [15:0]    quotient;
   reg [31:0]    dividend_copy, divider_copy, diff;
   wire [15:0]   remainder = dividend_copy[15:0];

   reg [4:0]     bit;
   wire          ready = !bit;

   initial bit = 0;

   always @( posedge clk )

     if ( ready && start ) begin

        bit = 16;
        quotient = 0;
        dividend_copy = {16'd0,dividend};
        divider_copy = {1'b0,divider,15'd0};

     end else begin

        diff = dividend_copy - divider_copy;
        quotient = { quotient[14:0], ~diff[31] };
        divider_copy = { 1'b0, divider_copy[31:1] };
        if ( !diff[31] ) dividend_copy = diff;
        bit = bit - 1;

     end

endmodule

module l07_test_div();
   wire [15:0] quot, rem;
   reg [15:0]  shadow_quot, shadow_rem;
   reg [15:0]  a, b;
   integer    i;
   parameter  num_tests = 1000;

   reg        clk;
   initial clk = 0;
   always #1 clk = ~clk;

   reg        start;
   wire       ready;

   wire [15:0] infinity;
   assign     infinity = 16'hffff;

   // simple_divider div(quot,rem,ready,a,b,start,clk);
   streamlined_divider div(quot,rem,ready,a,b,start,clk);

   initial begin

      # 0.5;

      while ( !ready ) #1;

      for (i=0; i<num_tests; i=i+1) begin:A

         integer shadow_quot, shadow_rem;

         a = $random;
         b = i & 1 ? $random : $random & 3;
         start = 1;

         while ( ready ) #1;

         start = 0;

         while ( !ready ) #1;

         shadow_quot = b ? a / b : infinity;
         shadow_rem  = b ? a % b : a;

         #1;
         if ( quot != shadow_quot || rem != shadow_rem ) begin
            $display("Wrong quot: %h / %h  =  %h r %h  !=  %h r %h (correct)",
                     a, b, quot, rem, shadow_quot, shadow_rem);
            $stop;
         end
      end

      $display("Tried %d divide tests",num_tests);
      $stop;
   end

endmodule'

Need help figuring the error

Answer 1

The string bit cannot be used as a signal name because it is a keyword. Refer to the IEEE Std 1800-2012 section "6.8 Variable declarations". It was added to the language in 2005.

You should change bit to something like my_bit (or something that has meaning to your design).