CODEWITHSUNDEEP
moduleverilogxorbitwise-xor
حبيبة أحمد
حبيبة أحمد

Reputation: 21

How can I run this code without syntax error?

This code gives me a syntax error when I run it on cmd. Any help?

module xor (a, b, c); 
 input a, b; 
 output c; 
 wire c, not_a, not_b; 
   not a_invert (not_a, a); 
   not b_invert (not_b, b); 
   and A1 (x, not_a, b); 
   and A2 (y, not_b, a); 
   or Result (c, x, y); 
endmodule 

module xor_test(a, b); //test bench
   input a, b;
   wire c;
   xor x(a,b,c);
   initial
   begin
      $monitor("c=%b",c);
   end
endmodule

module main();
   wire a=0, b=1 ; 
   xor_test t1(a,b);
endmodule

Upvotes: 2

Views: 62

Answers (1)

toolic
toolic

Reputation: 62073

You get a syntax error because you are trying to use xor as a module name. Since xor is a reserved keyword in Verilog, it is illegal to use it as a module name. You can rename it to something like xor1:

module xor1 (a, b, c); ////////// CHANGED
 input a, b; 
 output c; 
 wire c, not_a, not_b; 
   not a_invert (not_a, a); 
   not b_invert (not_b, b); 
   and A1 (x, not_a, b); 
   and A2 (y, not_b, a); 
   or Result (c, x, y); 
endmodule 

module xor_test(a, b); //test bench
   input a, b;
   wire c;
   xor1 x(a,b,c);  ////////// CHANGED
   initial
   begin
      $monitor("c=%b",c);
   end
endmodule

module main();
   wire a=0, b=1 ; 
   xor_test t1(a,b);
endmodule

I changed the 2 lines with comment CHANGED.

xor is a gate type, just like or, and and not in your code. Refer to IEEE Std 1800-2017, section 28. Gate-level and switch-level modeling.

Here is a running example on edaplayground

Upvotes: 2

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