CODEWITHSUNDEEP
verilog
NIN
NIN

Reputation: 209

error in verilog : warning using System verilog 'N bit vector?

I am using the Icarus compiler, and I'm doing a Mux 4:1.

The code is:

module mux (in,out,select);

input   [3:0] in;
input   [1:0] select;
output  reg out;

always@(select or in)
begin
    if (select == 2b'00)

        out = in[0];
    end 

    else if (select == 2b'01)
    begin
        out = in[1];
    end

    else if (select == 2b'10)
    begin   
        out = in[2];
    end

    else if (select == 2b'11)
    begin
        out = in[3];
    end

end
endmodule

But, I get this message from the compiler:

enter image description here

Is the problem because I'm using bit format inside "if" expression instead of "int" expression?

Upvotes: 1

Views: 2388

Answers (2)

dave_59
dave_59

Reputation: 42788

The problem with your code is you are writing 2b'00 instead of 2'b00 and Icarus is getting confused thinking you are writing SystemVerilog code, which is not correct either. So either fix your literals, or write your code more efficently as Morgan has posted.

Upvotes: 2

Morgan
Morgan

Reputation: 20554

Try (with verilog 2005 or later):

module mux (  
  input       [3:0] in,
  input       [1:0] select,
  output  reg       out
);
  always @* begin
    out = in[select];
  end
endmodule

Upvotes: 1

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