CODEWITHSUNDEEP
cpu-architecturedma
Agent007
Agent007

Reputation: 51

Direct Memory Access

I have this basic doubt about DMA. When the CPU has relinquished the bus for DMA to carry on with data fetching/ storing, how does it continue processing?

I mean even the CPU's got to get it instructions, store back results to the memory/IOs through the bus, does it not?

Upvotes: 2

Views: 1404

Answers (2)

Peter Cordes
Peter Cordes

Reputation: 365457

CPUs have cache, so they can do a lot without any actual main-memory accesses. Even low-power systems tend to have caches, because driving signals off-chip costs enough energy that a cache pays for itself in energy saved by cache hits.

More importantly, DMA doesn't "take over" the RAM, or even necessarily saturate memory bandwidth. The CPU doesn't "relinquish the bus"; the memory controller accepts read/write requests from the CPU core(s) and other system devices. Running a memory-heavy task on the CPU will slow down delay DMA, as well as the other way around, as the memory controller or system agent arbitrates access to memory, queuing read and write requests from all sources.

DMA is great for transfers that are still much slower than memory bandwidth. For example SATAIII is 6 Gbits/s, while main memory bandwidth for dual-channel DDR3-1600MHz is about 25 GBytes/s. So programmed-io would spend most of its time waiting for data from the SATA controller, not even bottlenecked on storing to RAM.

An example of how the pieces fit together in a modern Intel x86 CPU: this diagram of Intel Skylake's system architecture (including eDRAM as memory-side cache). Sorry I didn't find a simpler diagram showing just the cores and system agent, but in a system without eDRAM, the only thing to the right of the system agent is the memory controller, and everything else stays the same.

The memory controller is on-die, so the only off-chip connection in this diagram is the PCIe bus, and the DDR4 bus between memory controller (MC) and DRAM.

Skylake system agent diagram, from IDF via ARStechnica

Upvotes: 8

coder23
coder23

Reputation: 43

There are two basic types of DMA usage models. First is when a CPU is waiting for the DMA to finish - SYNCed operation or a blocking DMA call. The other is when the CPU makes an ASYNC (or non-blocking) DMA request. This lets CPU continue with the regular control flow. This way it can off-load work to DMA to do something more important.

If I understand your question correctly, and as Peter said, when a CPU has made a non-blocking DMA request, and the DMA is actively doing something on the bus, still CPU can do all the regular operations including accessing the RAM because the bus can have multiplexed traffic. Or in other words the bus can handle multiple masters at the same time.

The coherency and consistency, which makes things little more complicated, are generally maintained using the right programming paradigms based on the hardware support.

Upvotes: 1

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