CODEWITHSUNDEEP
system-verilogverificationuvm
sara8d
sara8d

Reputation: 413

creating test bench for AXI bus

I have to creat test bench to my project which contains AXI bus.

I start to write the interface and the transaction for write and read. I read the following blog: http://blog.verificationgentleman.com/2016/08/testing-uvm-drivers-part-2.html?showComment=1471877179631#c7809781639091671746

According this blog the interface should be:

interface vgm_axi_interface(input bit ACLK, input bit ARESETn);
  logic [3:0] AWID;
  logic [31:0] AWADDR;
  logic [3:0] AWLEN;
  logic AWVALID;
  logic AWREADY;


  logic [3:0] WID;
  logic [31:0] WDATA;
  logic WLAST;
  logic WVALID;
  logic WREADY;

  logic [3:0] BID;
  logic [1:0] BRESP;
  logic BVALID;
  logic BREADY;
endinterface

What about all the other signals (for example ARBURST,ARLOCK,ARCACHE,ARPROT,ARQOS,ARREGION)? There are many more signal according the specification of AXI4.

In addition are the following properties in the transaction are enough for write transaction?

typedef enum bit [3:0] { LENGTH_[1:16] } length_e;


class sequence_item extends uvm_sequence_item;
  rand bit [3:0] id;
  rand bit [31:0] address;
  rand length_e length;
  rand transfer transfers[];
  rand int unsigned delay;
endclass


class transfer extends uvm_sequence_item;
  rand bit[31:0] data;
  rand int unsigned delay;
endclass

Upvotes: 1

Views: 2259

Answers (1)

Kamil Rymarz
Kamil Rymarz

Reputation: 408

Signals in this interface contains only minimum set of signals that are required to perform single write operation on AXI bus with fixed size and burst type. If yours DUT supports more than only simple write then you have to add other signals. For example if you would like to test read operation then you also have to add all signals that are required for read address channel and read data channel.

Some of AXI signals can be omitted only if you know that your design will not support it. If you support different burst type in write operations then you have to add AWBURST signal to the interface and also to the transaction.

Upvotes: 3

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