CODEWITHSUNDEEP
veriloghdl
archity
archity

Reputation: 612

8bit adder not working properly

I'm writing a Verilog code to construct an 8 bit adder using 8 full adder. That 8 bit adder should add 2 incoming inputs each of 8 bit bus. Here's the code for the single full adder:

module FullAdder(
input a_,
input b_,
input cin_,
output sout_,
output cout_
);
wire temp1, temp2, temp3;

assign sout_ = a_ ^ b_ ^ cin_;
assign cout_ = ((a_ & b_) | (b_ & cin_) | (cin_ & a_));

endmodule

And here's the code for the 8 bit adder modue which will call the full adder 8 times.

module EightBitAdder(
input [7:0] a,
input [7:0] b,
//input cin,
output cout,  //carry; will be sent as OP, but won't be further used.
output [7:0] sout  //sum, sent as OP
);

wire try;

begin 
FullAdder mg0(.a_(a[0]), .b_(b[0]), .cin_(0), .cout_(try), .sout_(sout[0]));
FullAdder mg1(.a_(a[1]), .b_(b[1]), .cin_(try), .cout_(try), .sout_(sout[1]));
FullAdder mg2(.a_(a[2]), .b_(b[2]), .cin_(try), .cout_(try), .sout_(sout[2]));
FullAdder mg3(.a_(a[3]), .b_(b[3]), .cin_(try), .cout_(try), .sout_(sout[3]));
FullAdder mg4(.a_(a[4]), .b_(b[4]), .cin_(try), .cout_(try), .sout_(sout[4]));
FullAdder mg5(.a_(a[5]), .b_(b[5]), .cin_(try), .cout_(try), .sout_(sout[5]));
FullAdder mg6(.a_(a[6]), .b_(b[6]), .cin_(try), .cout_(try), .sout_(sout[6]));
FullAdder mg7(.a_(a[7]), .b_(b[7]), .cin_(try), .cout_(try), .sout_(sout[7]));
end
endmodule

The problem is that the output is not showing correctly. It always displays the first bit and then fills up the rest of the bits with don't cares (X). What could be the problem here ?

Upvotes: 0

Views: 3676

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

The same try wire is driven by all the 8 full adders, so this is very likely to result in an X value if both driven with 0 and 1 from the full-adder carry out.

Consider making a carry out wire instead, like:

wire [7:0] cout;

and use the different bits for the different full adders, like:

FullAdder mg0(.a_(a[0]), .b_(b[0]), .cin_(0), .cout_(cout[0]), .sout_(sout[0]));
FullAdder mg1(.a_(a[1]), .b_(b[1]), .cin_(cout[0]), .cout_(cout[1]), .sout_(sout[1]));
...

Upvotes: 1

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