CODEWITHSUNDEEP
system-verilog
Halil İbrahim Azak
Halil İbrahim Azak

Reputation: 15

SystemVerilog Array Index

i have a module like this:

module ArrayTest(input logic clk, [9:0] sindex, output shortint OBYTE);
shortint ima_step_table[89] = { 
    7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 
    19, 21, 23, 25, 28, 31, 34, 37, 41, 45, 
    50, 55, 60, 66, 73, 80, 88, 97, 107, 118, 
    130, 143, 157, 173, 190, 209, 230, 253, 279, 307,
    337, 371, 408, 449, 494, 544, 598, 658, 724, 796,
    876, 963, 1060, 1166, 1282, 1411, 1552, 1707, 1878, 2066, 
    2272, 2499, 2749, 3024, 3327, 3660, 4026, 4428, 4871, 5358,
    5894, 6484, 7132, 7845, 8630, 9493, 10442, 11487, 12635, 13899, 
    15289, 16818, 18500, 20350, 22385, 24623, 27086, 29794, 32767 
};
initial begin
    OBYTE <= -1;
end

always@ (posedge clk) begin
    OBYTE = ima_step_table[sindex];
end
endmodule

I am using Digilent Basys3 board and clk is its clock. sindex is switches on fpga and it shows output OBYTE with leds. Problem is it does not show the correct value. It shows 7, the first value, when sindex is between 88-95 or 120-127, meaning when sindex[6], [4], [3] are 1. For any other sindex value it shows 0. I have no idea why this is happening.

Thanks for any help.

Upvotes: 0

Views: 1957

Answers (1)

dave_59
dave_59

Reputation: 42788

I think how you model and initialize an array as a loop-up table depends on the level of SystemVerilog support from your synthesis tool. In SystemVerilog, I would have at declared ima_step_table as a parameter or const to indicate that it is never to be written to. But many synthesis tools still only support Verilog-1995 syntax which only gives you the choice of an initial block to initialize an array. Verilog-2001 added variable declaration initializations, but not for arrays. SystemVerilog added array literals and the ability to declare an array as a parameter or const

Upvotes: 0

Related Questions