CODEWITHSUNDEEP
filterverilogsignal-processingsystem-verilog
digitalman
digitalman

Reputation: 1

Array manipulation in systemverilog

logic [M-1:0] x [N-1:0]; // x is N number of rows and M number of bits
genvar i;
genvar j;

for (i=0; i<N; i++) begin
     for (j=0; j<M; j++) begin
         x[i][j] = $random;
     end
end

In the real code, it is not random, but this is an input bit. But the same error is introduced which is

token is '['
x[i][j]

making a pointer on the second [

What is the mistake?

Upvotes: 0

Views: 157

Answers (2)

Serge
Serge

Reputation: 12354

It is strange that you use a generate construct to initialize an array in a purely behavioral way. The construct is used to simply replicate verilog statements, such as assign or module instances.

Usually such initialization is done in initial blocks, like the following:

initial begin
  for (int i=0; i<N; i++) begin
     for (int j=0; j<M; j++) begin
         x[i][j] = $random;
     end
  end
end

Upvotes: 1

toolic
toolic

Reputation: 62037

Since you have a generate construct, you can not have a bare assignment statement there. Use the assign keyword:

for (i=0; i<N; i++) begin
     for (j=0; j<M; j++) begin
         assign x[i][j] = $random;
     end
end

Upvotes: 1

Related Questions