CODEWITHSUNDEEP
verilog
Fakhrul islam
Fakhrul islam

Reputation: 13

Verilog: Loop count limit exceeded. Condition is never false

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Can anyone here help me to remove this error of loop limit exceed? The Databits is defined in another module in "constant.v". The length of Databits is 64. I have uploaded a picture for reference 1. It has the pLayer "permutation layer" used in cipher under Shannon confusion and diffusion theory.

Basically, I need to change the Position of each bit of input state of cipher, that consists of 64 bits. So if the bit '0' or '1' is in 1st position the output position should be 16, 2nd bit should be reposition to 32nd position, and likewise. The code is also in the same link.

Upvotes: 1

Views: 2564

Answers (1)

Brad Budlong
Brad Budlong

Reputation: 1785

I see at least two problems in your code:

1) You have reg k; and that is being used as you for loop counter. That is just a single bit, so it isn't going to count up to 63. That means that it is always <= 63 and the loop is infinite. You can define it as an integer or a reg [6:0]. Make sure you don't make it a 6 bit register, because that will just go to 63 and once again the loop will be infinite.

2) The second problem is that you calculate the result for each bit and then you overwrite all the previous results and loop around again. You need to build up the results for each bit. One approach that is similar to your code would be:

temp = 0;
for(k=0; k<=63;k=k+1) begin
  position = (4*k) % 63;
  if (k == 63) position = 63;
  else temp |= ((statein>>k) & 1'b1) << position;
end
stateout = temp;

Alternatively you could just use indexing in the else:

temp[position] = statein[k];

Upvotes: 3

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