CODEWITHSUNDEEP
verilogmodelsim
Someone
Someone

Reputation: 1

Verilog model sim

I want to split a verilog program in a module that will be called from a top. This is a counter that displays the output,and every bit.

module file1(output reg b3,
 output reg b2,
  output reg b1,
 output reg b0,
output reg[3:0]y);

reg clock;
initial begin
  clock=0;
  b0=0;
  b1=0;
  b2=0;
  b3=0;
  y=0;
  forever #5 clock= ~clock;
end
always @(posedge clock)
    begin
    y=y+1;
    b0=y[0];
    b1=y[1];
    b2=y[2];
    b3=y[3];
    end
endmodule

This is how I split the program in a module called by top. MODULE

module modul(input reg clock,
output reg b3,
output reg b2,
output reg b1,
output reg b0,  
output reg[3:0]y
);
always @(posedge clock)
    begin
    y=y+1;
    b0=y[0];
    b1=y[1];
    b2=y[2];
    b3=y[3];
    end
endmodule

TOP

 `timescale 1ns/1ps
    module testare_modul;
    reg clock; wire clock1;
    reg b3;   
    reg b2;
    reg b1;
    reg b0;  
    reg [3:0]y;
    modul lol(
    .clock(clock),
    .y(y),
    .b3(b3),
    .b2(b2),
    .b1(b1),
    .b0(b0)
    );
    initial begin
      clock=0;
      b0=0;
      b1=0;
      b2=0;
      b3=0;
      y=0;
      forever #5 clock= ~clock;
    end
    endmodule

I have 0 errors when compilling but when I try to simulate I get Illegal output or inout port connection.I am new to these language and I would appreciate your help a lot!

Upvotes: 0

Views: 116

Answers (2)

Prashant
Prashant

Reputation: 362

There are a couple of things here. In modul, you have defined clock as input reg. Inputs cannot be reg. they are just inputs. So clk has to be defined as

input clock,

Secondly, you have defined y as an output reg, but it is also an input, as you are driving the value of y from the top module. If you do need this functionality, then y needs to be defined as an inout. However if it is declared as an inout, then it cannot be driven always, you need some other signal that controls when the port is an input and being tri-stated by the driver inside modul, and when is modul driving the port i.e. an putput, so that it has to be tristated in the top module's driver.

It would be better if you explain what is the functionality you are trying to achieve in this design to allow the community to help.

Mind you wires reg and ports on modules in verilog are way different from function parameters being passed in 'C'

Upvotes: 0

Matthew
Matthew

Reputation: 13937

Surely this output reg[3:0]y should be this input reg[3:0]y?

Upvotes: 0

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