CODEWITHSUNDEEP
verilogfpga
fadedbee
fadedbee

Reputation: 44765

How to get a faster clock in verilog on a Lattice iCEstick?

The stick has a 12MHz oscillator on board. http://www.latticesemi.com/icestick

I have managed to write verilog code to divide this clock down and flash LEDs are 1Hz. (I am just starting to learn verilog.)

I believe that this FPGA will work at up to 133MHz.

Is there a way to generate a faster clock signal (in verilog) from the 12MHz oscillator?

Upvotes: 0

Views: 2271

Answers (2)

Shiva Shankar
Shiva Shankar

Reputation: 76

I have used a higher clock frequency to display a pong game in a VGA monitor using TinyFPGA BX. The TinyFPGA BX and the Lattice iCEstick are quite similar. Therefore, I would like to share my code. You may need to use the official Lattice software for an easier GUI (Graphical User Interface) configuration. https://www.latticesemi.com/software

module top(
input wire clk_16,
output USBPU
);

assign USBPU = 0; // drive USB pull-up resistor to '0' to disable USB 
output wire;
SB_PLL40_CORE #(
                .FEEDBACK_PATH("SIMPLE"),
                .DIVR(4'b0000),         // DIVR =  0
                .DIVF(7'b0110001),      // DIVF = 49
                .DIVQ(3'b101),          // DIVQ =  5
                .FILTER_RANGE(3'b001)   // FILTER_RANGE = 1
        ) uut (
                .LOCK(locked),
                .RESETB(1'b1),
                .BYPASS(1'b0),
                .REFERENCECLK(clk_16),  // clk_16_MHz is the original clock
                .PLLOUTCORE(clk)        // clk is the modified clock with higher frequency
                );

Upvotes: 0

fadedbee
fadedbee

Reputation: 44765

Answer not yet tested.

Via https://www.reddit.com/r/yosys/comments/3yrq6d/are_plls_supported_on_the_icestick_hw/

From: https://github.com/SubProto/icestick-vga-test/blob/master/vga.v 

wire clk;

  SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
                  .PLLOUT_SELECT("GENCLK"),
                  .DIVR(4'b0001),
                  .DIVF(7'b1000010),
                  .DIVQ(3'b100),
                  .FILTER_RANGE(3'b001),
                 ) uut (
                         .REFERENCECLK(pclk),
                         .PLLOUTCORE(clk),
                         .LOCK(D5),
                         .RESETB(1'b1),
                         .BYPASS(1'b0)
);

Also:

iCE40 sysCLOCK PLL The iCE40 Phase Locked Loop (PLL) provides a variety of user-synthesizable clock frequencies, along with cus- tom phase delays.The PLL in the iCE40 device can be configured and utilized with the help of software macros or the PLL Module Generator. The PLL Module Generator utility helps users to quickly configure the desired settings with the help of a GUI and generate Verilog code which configures the PLL macros. Figure 2 shows the iCE40 sys- CLOCK PLL block diagram.

http://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/IK/iCE40sysCLOCKPLLDesignandUsageGuide.pdf?document_id=47778

Upvotes: 2

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