CODEWITHSUNDEEP
vhdl
Wile E Coyote
Wile E Coyote

Reputation: 71

how to have the vdhl code add text to itself

While trying to see if I could come up with a way to make the number of outputs variable by setting a "generic" I came up with the following thought. The idea would be to have a routine in the VHDL code inside the "port" declaration such that the routine would add the text "output(X) : out std_logic_vector(bits-1 downto 0); inside the "port" declaration. Please note that (X) represents the number of the output ports, i.e. output1, output2, etc. The idea being that when the VHDL parser reads the code it would see the required number of outputs when compiled. Is this something that can be done?

Upvotes: 1

Views: 150

Answers (1)

FRob
FRob

Reputation: 4041

If I understood you correctly, you want to do meta-programming and have a generic number of ports. That's not possible in VHDL. However, you can just use a multidimensional array for that:

-- declare array type VHDL-2008-style
-- put this in a package
type slv_array is array(natural range<>) of std_logic_vector;

entity test is
generic (
    -- number of outputs, at least one output
    num_outputs : positive := 1
);
port (
    my_inputs  : in  std_logic_vector(1 downto 0);
    my_outputs : out slv_array(num_outputs - 1 downto 0)(1 downto 0)
);
end entity test;

You would then be able to use the component like this:

comp0 : component test
    generic map (
        num_outputs => 1
        )
    port map (
        my_inputs => "10",
        my_outputs(0) => my_output0
        );

comp1 : component test
    generic map (
        num_outputs => 2
        )
    port map (
        my_inputs => "00",
        my_outputs(0) => my_output1
        my_outputs(1) => my_output2
        );

Upvotes: 2

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