CODEWITHSUNDEEP
vhdlfpgaintel-fpga
Raul Juliao
Raul Juliao

Reputation: 55

VHDL buffer variable vs out variable

I work in a VHDL program and I need to do a RAM 256 using the ALTERA DE2-115. The outputs will show in a seven segment display. The problem is that: I have a dataout output variable. Then the variable has the following values of the temp_ram array:

dataout <= temp_ram(conv_integer(dir));

Then I want to divide the vaules of dataout to put in the seven segment

dataout(7 downto 4)
dataout(3 downto 0)

This shows the following error:

Error (10309): VHDL Interface Declaration error in RAM.vhd(45): interface object "dataout" of mode out cannot be read. Change object mode to buffer.

When I change to buffer and this run prefect, but I can't understand what happen

Upvotes: 2

Views: 8305

Answers (2)

Erik Vanendert
Erik Vanendert

Reputation: 36

For cross-platform compatibility and code-reusability, I'd recommend an intermediate signal ( dataout_int can be used by other statements) :

    dataout_int <= temp_ram(conv_integer(dir));

and assign the output to this intermediate signal:

    dataout <= dataout_int;

Upvotes: 2

Paebbels
Paebbels

Reputation: 16211

You are using conv_integer from a Synopsys package. Please use only official IEEE packages.

dataout is a signal, not a variable, because you use a signal assignment statement. Moreover, the signal is a port of mode out. (Ports are signals as well).

Besides static typing, VHDL is also checking directions of signal in ports. Your signal is of mode out so it can't be read.

Als a solution, you can:

  • use an intermediate signal,
  • use mode buffer, which is not supported by all synthesis tools equally
  • use VHDL-2008, which allows ports of mode out to be read.

Quartus support some VHDL-2008 features.

Upvotes: 2

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