CODEWITHSUNDEEP
scalahardwarechisel
SpaceCowboy max
SpaceCowboy max

Reputation: 137

chisel-testers SteppedHWIOTester with multi clock domains

Trying to test asyncFifo wrote in chisel with SteppedHWIOTester like that

class AsyncFifo(width: Int, depth: Int, syncStages: Int) extends Module {
  val length = log2Ceil(depth)
  val io = IO(new Bundle {
    val clk_write = Input(Clock())
    val clk_read = Input(Clock())
    val rstn_write = Input(Bool())
    val rstn_read = Input(Bool())
    val deq = Decoupled(UInt(width.W))
    val enq = Flipped(Decoupled(UInt(width.W)))
  })
  val memory = Mem(depth, UInt(width.W))
  val reader: reader = withClock(io.clk_read)( Module(new reader(width, depth, syncStages)) )
  val writer: writer = withClock(io.clk_write)( Module(new writer(width, depth, syncStages)) )
  //some connections here...
}
class AsyncFifoHardWareTester extends SteppedHWIOTester {
  val device_under_test = Module(new AsyncFifo(32, 32, 2))
  val c = device_under_test
  enable_all_debug = true

  step(2)
  poke(c.io.enq.bits, 0x11L)
  poke(c.io.enq.valid, 0x1L)
  step(2)
  poke(c.io.enq.bits, 0x11L)
  poke(c.io.enq.valid, 0x0L)
  step(2)
  expect(c.io.deq.valid, 0x11L)
  expect(c.io.deq.bits, 0x0L)
}

Tester generates vcd, where clk_write and clk_read are driven by zero. Is there any way to declare async clocks and theirs ratio in HW or in PeekPoke testers?

Upvotes: 3

Views: 252

Answers (1)

Chick Markley
Chick Markley

Reputation: 4051

Unfortunately, the answer at the moment is no, the chisel-testers repo does not have the facilities for testing multiple clocks. The chisel team is working hard on a cleanup and improvement of the chisel-testers, See: Chisel3 Issues: Testers Unification to see some of the motivating discussion. Also in progress is a re-write of the firrtl interpreter that will have explicit support for multiple clocks, but that's probably a couple of months away.

People have done this on their own. You might also try this question on Chisel Users Group

Upvotes: 2

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