CODEWITHSUNDEEP
hardwarevhdl
Richard23
Richard23

Reputation: 139

Subprocedure call in VHDL

I have two nested procedures, where the "main" procedure makes use of "subproc" to accumulates a result in variables t0 and t1, which is then returned at the end. This should all be computed in one clock cycle, and the circuit more or less just consists of simple logic gates (xor, or, and). When I try to describe the circuit as below I get the following error:

Acutal (variable t0) for formal "a" is not a signal

That makes sense as the subprocure requires signals as input, but I wanna pass it a variable during the main procedure. Is there a simple way to circumvent this problem with casting for example?

Thanks

procedure subproc
(
  signal a : in  std_logic_vector(31 downto 0);
  signal b : in  std_logic_vector(31 downto 0);
  signal c : in  std_logic_vector(31 downto 0);
  signal d : in  std_logic_vector(31 downto 0);    
  signal e : out std_logic_vector(31 downto 0);
  signal f : out std_logic_vector(31 downto 0)    
)
is
  variable x : std_logic_vector(31 downto 0);
  variable y : std_logic_vector(31 downto 0);    
begin

  x := (others => '0');
  y := (others => '0');

  for i in 0 to 31 loop
      x(i) := (a(i) xor b(i)) and (c(i) xor d(i));
      y(i) := (a(i) xor b(i)) or ((d(i) xor c(i)) xor b(i));
  end loop;

  e <= x(31 downto 0);
  f <= y(31 downto 0);

end;

procedure main
(
  signal a : in  std_logic_vector(31 downto 0);
  signal b : in  std_logic_vector(31 downto 0);
  signal r : out std_logic_vector(31 downto 0)
)
is
  variable res : std_logic_vector(31 downto 0);
  variable t0, t1 : std_logic_vector(31 downto 0);
  constant c : std_logic_vector(31 downto 0) := X"fedcba90";
  constant d : std_logic_vector(31 downto 0) := X"7654321f";       
begin

  t0 := (others => '0');
  t1 := (others => '0');

  for i in 0 to 31 loop
    if ( (c(i) = '0') && (d(i) = '1') ) then
       subproc( t0, t1, 
                a, b, t0, t1 );
    end if;              
  end loop;

  r <= t0;
end;

Upvotes: 0

Views: 1187

Answers (2)

Philippe
Philippe

Reputation: 3730

First off, your "if" clause is written in C-style. You want to say:

if (c(i) = '0') and (d(i) = '1') then

But the problem really is that you describe the procedure as taking SIGNALs as arguments. If you want the results to be assigned to variables, you need to declare a different procedure signature:

procedure subproc (
signal a : in  std_logic_vector(31 downto 0);
signal b : in  std_logic_vector(31 downto 0);
signal c : in  std_logic_vector(31 downto 0);
signal d : in  std_logic_vector(31 downto 0);
variable e : out std_logic_vector(31 downto 0);
variable f : out std_logic_vector(31 downto 0))

But then, you also need to change all assignments to e and f, so that they are variable assignments:

e := x(31 downto 0);

Upvotes: 2

Charles Steinkuehler
Charles Steinkuehler

Reputation: 3365

Why don't you just define the subproc parameters as variables instead of signals?

Upvotes: 0

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