CODEWITHSUNDEEP
vhdl
Rohit Kumar
Rohit Kumar

Reputation: 1

How to use a function/task which is declared within a sub module in VHDL

how can I use a function(function_a) declared within an entity (module_calling_fn_a), from another top entity(module_top) which has an instantiation of module_calling_fn_a.

This is possible in verilog, by the following module_calling_fn_a. function_a ();

Is it possible in VHDL ?

Upvotes: 0

Views: 360

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

The function will be local to module_calling_fn_a module, and cant't be used from another module.

Instead, to have the same function available in both modules, create a package and use that package in both modules.

Upvotes: 2

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