CODEWITHSUNDEEP
vhdl
Pepelee
Pepelee

Reputation: 453

Synchronization of two processes

my architecture uses a square root component, which has following ports:

component SQRT is
    port (sqrt_clock : in  std_logic;
          start      : in  std_logic;
          value      : in  std_logic_vector (15 downto 0);
          result     : out std_logic_vector (7 downto 0);
          busy       : out std_logic
          );
  end component;

When the sqrt-module finishes its work, the busy signal will be '0'

In my main process, I am iterating through an input array and calculate two integers a and b, which are the inputs of my square root module. Then, I want to fill a second data array with the output files, which has the same array size as the input array

Main_Process: process(clk)
  variable a : integer := 0;
  variable b : integer := 0;
begin
if reset = '0'then
...
elsif clk'event and clk = '1' then
for iter in 0 to arraySize-1 loop
 -- x and y calculation with inputarray(iter)
   value      <= std_logic_vector(TO_UNSIGNED(a+b, 16));
   start      <= '1';
   outputarray(iter) <= TO_INTEGER(unsigned(sqrt_output)); 
end loop;     
end case;
end process;

I want the main process to wait until the sqrt-module has finished its calculation after each array-iteration. Without any synchronization, the first result from the sqrt-module gets filled in all the output-array elements. With the right behavior, the main process should wait until the sqrt-module finished its calculation, then fill the output-array element and in the final step continue with the for loop and so on.

I tried putting the "busy"-signal in the main-process' sensitivity list:

 Main_Process: process(clk, busy)
      variable a : integer := 0;
      variable b : integer := 0;
    begin
    if reset = '0'then
    ...
    elsif clk'event and clk = '1' then

   --only iterate further then sqrt is finished (busy = 0)
    for iter in 0 to arraySize-1 loop
     -- x and y calculation with inputarray(iter)
       value      <= std_logic_vector(TO_UNSIGNED(a+b, 16));
       start      <= '1';
       if busy = '0' then
          outputarray(iter) <= TO_INTEGER(unsigned(sqrt_output)); 
          start <= '0';
       end if;
    end loop;         
    end if;
    end process;

Unfortunately, it does not work. Is there a simple way to implement a sync. without a third FSM process?

note: I want the code to be also synthesizable.

Upvotes: 1

Views: 1380

Answers (1)

xvan
xvan

Reputation: 4855

At your reduced example, you don't need the clock signal at main so you may delete the sensitivity list. 

wait until busy = '0'
outputarray(iter) <= TO_INTEGER(unsigned(sqrt_output)); 
start <= '0';

Another alternative is to replace the for loop with a while

variable iter : integer range 0 to arraySize;

variable first : boolean;

[...]
iter := 0;
first := true;
while iter < arraySize loop
   if busy = '0' then
      if first = false then          
        outputarray(iter) <= TO_INTEGER(unsigned(sqrt_output)); 
        start <= '0';
      end if

 -- x and y calculation with inputarray(iter)
   value      <= std_logic_vector(TO_UNSIGNED(a+b, 16));
   start      <= '1';

   first := false;
   iter := iter + 1;

   end if
end loop;

Upvotes: 2

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